Load single 1-element structure and replicate to all lanes of one register loads one element from memory into every element of one or two vectors. For details of the addressing mode, see Advanced SIMD addressing mode.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | D | 1 | 0 | Rn | Vd | 1 | 1 | 0 | 0 | size | T | a | Rm | ||||||||||
if size == '11' || (size == '00' && a == '1') then UNDEFINED; constant ebytes = 1 << UInt(size); constant regs = if T == '0' then 1 else 2; constant alignment = if a == '0' then 1 else ebytes; constant d = UInt(D:Vd); constant n = UInt(Rn); constant m = UInt(Rm); constant wback = (m != 15); constant register_index = (m != 15 && m != 13); if n == 15 || d+regs > 32 then UNPREDICTABLE;
If d+regs > 32, then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | D | 1 | 0 | Rn | Vd | 1 | 1 | 0 | 0 | size | T | a | Rm | ||||||||||
if size == '11' || (size == '00' && a == '1') then UNDEFINED; constant ebytes = 1 << UInt(size); constant regs = if T == '0' then 1 else 2; constant alignment = if a == '0' then 1 else ebytes; constant d = UInt(D:Vd); constant n = UInt(Rn); constant m = UInt(Rm); constant wback = (m != 15); constant register_index = (m != 15 && m != 13); if n == 15 || d+regs > 32 then UNPREDICTABLE;
If d+regs > 32, then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VLD1 (single element to all lanes).
| <c> |
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. |
|
For encoding T1: see Standard assembler syntax fields. |
| <q> |
| <size> |
Is the data size,
encoded in
|
| <Rn> |
Is the general-purpose base register, encoded in the "Rn" field. |
| <align> |
When <size> == 8, <align> must be omitted, otherwise it is the optional alignment. Whenever <align> is omitted, the standard alignment is used, see Unaligned data access, and is encoded in the "a" field as 0. Whenever <align> is present, the permitted values and encoding depend on <size>:
: is the preferred separator before the <align> value, but the alignment can be specified as @<align>, see Advanced SIMD addressing mode. |
| <Rm> |
Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field. |
For more information about the variants of this instruction, see Advanced SIMD addressing mode.
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); constant address = R[n]; constant boolean nontemporal = FALSE; constant boolean tagchecked = FALSE; constant AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked); if !IsAligned(address, alignment) then AArch32.Abort(address, AlignmentFault(accdesc)); constant integer esize = 8 * ebytes; constant bits(esize) element = MemU[address,ebytes]; constant bits(64) replicated_element = Replicate(element, 64 DIV esize); for r = 0 to regs-1 D[d+r] = replicated_element; if wback then if register_index then R[n] = R[n] + R[m]; else R[n] = R[n] + ebytes;
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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