VMLA (floating-point) -- AArch32

Vector Multiply Accumulate multiplies corresponding elements in two vectors, and accumulates the results into the elements of the destination vector.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .

if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED; if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; constant advsimd = TRUE; constant add = (op == '0'); constant integer esize = 32 >> UInt(sz); constant integer elements = 64 DIV esize; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm); constant regs = if Q == '0' then 1 else 2;

if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; if size == '01' && cond != '1110' then UNPREDICTABLE; if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; constant advsimd = FALSE; constant add = (op == '0'); constant integer esize = 8 << UInt(size); integer d; integer n; integer m; case size of when '01' d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '10' d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '11' d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); constant boolean floating_point = boolean UNKNOWN; constant integer regs = integer UNKNOWN; constant integer elements = integer UNKNOWN;

CONSTRAINED UNPREDICTABLE behavior

If size == '01' && cond != '1110', then one of the following behaviors must occur:

if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED; if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; if sz == '1' && InITBlock() then UNPREDICTABLE; constant advsimd = TRUE; constant add = (op == '0'); constant integer esize = 32 >> UInt(sz); constant integer elements = 64 DIV esize; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm); constant regs = if Q == '0' then 1 else 2;

CONSTRAINED UNPREDICTABLE behavior

if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; if size == '01' && InITBlock() then UNPREDICTABLE; if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; constant advsimd = FALSE; constant add = (op == '0'); constant integer esize = 8 << UInt(size); integer d; integer n; integer m; case size of when '01' d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '10' d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '11' d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); constant boolean floating_point = boolean UNKNOWN; constant integer regs = integer UNKNOWN; constant integer elements = integer UNKNOWN;

CONSTRAINED UNPREDICTABLE behavior

Assembler Symbols

<c>	For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional.
	For encoding A2, T1 and T2: see Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<dt>

Is the data type for the elements of the vectors, encoded in sz:

sz	<dt>
0	F32
1	F16

<Qd>	Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qn>	Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>	Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>	Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>	Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>	Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.

<Sd>	Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sn>	Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

<Sm>	Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDOrVFPEnabled(TRUE, advsimd); if advsimd then // Advanced SIMD instruction constant FPCR_Type fpcr = StandardFPCR(); for r = 0 to regs-1 for e = 0 to elements-1 addend = FPMul(Elem[D[n+r],e,esize], Elem[D[m+r],e,esize], fpcr); if !add then addend = FPNeg(addend, fpcr); Elem[D[d+r],e,esize] = FPAdd(Elem[D[d+r],e,esize], addend, fpcr); else // VFP instruction constant FPCR_Type fpcr = EffectiveFPCR(); case esize of when 16 addend16 = FPMul(H[n], H[m], fpcr); if !add then addend16 = FPNeg(addend16, fpcr); H[d] = FPAdd(H[d], addend16, fpcr); when 32 addend32 = FPMul(S[n], S[m], fpcr); if !add then addend32 = FPNeg(addend32, fpcr); S[d] = FPAdd(S[d], addend32, fpcr); when 64 addend64 = FPMul(D[n], D[m], fpcr); if !add then addend64 = FPNeg(addend64, fpcr); D[d] = FPAdd(D[d], addend64, fpcr);

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05