Move SIMD&FP Special register to general-purpose register moves the value of an Advanced SIMD and floating-point System register to a general-purpose register. When the specified System register is the FPSCR, a form of the instruction transfers the FPSCR.{N, Z, C, V} condition flags to the APSR.{N, Z, C, V} condition flags.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
When these settings permit the execution of Advanced SIMD and floating-point instructions, if the specified floating-point System register is not the FPSCR, the instruction is undefined if executed in User mode.
In an implementation that includes EL2, when HCR.TID0 is set to 1, any VMRS access to FPSID from a Non-secure EL1 mode that would be permitted if HCR.TID0 was set to 0 generates a Hyp Trap exception. For more information, see ID group 0, Primary device identification registers.
For simplicity, the VMRS pseudocode does not show the possible trap to Hyp mode.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | reg | Rt | 1 | 0 | 1 | 0 | (0) | (0) | (0) | 1 | (0) | (0) | (0) | (0) | |||||||||
| cond | |||||||||||||||||||||||||||||||
constant t = UInt(Rt); if !(reg IN {'000x', '0101', '011x', '1000'}) then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 if t == 15 && reg != '0001' then UNPREDICTABLE;
If !(reg IN {'000x', '0101', '011x', '1000'}), then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | reg | Rt | 1 | 0 | 1 | 0 | (0) | (0) | (0) | 1 | (0) | (0) | (0) | (0) | ||||||
constant t = UInt(Rt); if !(reg IN {'000x', '0101', '011x', '1000'}) then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 if t == 15 && reg != '0001' then UNPREDICTABLE;
If !(reg IN {'000x', '0101', '011x', '1000'}), then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rt> |
Is the general-purpose destination register, encoded in the "Rt" field. Is one of: |
if ConditionPassed() then EncodingSpecificOperations(); if reg == '0001' then // FPSCR CheckVFPEnabled(TRUE); if t == 15 then PSTATE.<N,Z,C,V> = FPSR.<N,Z,C,V>; else R[t] = FPSCR; elsif PSTATE.EL == EL0 then UNDEFINED; // Non-FPSCR registers accessible only at PL1 or above else CheckVFPEnabled(FALSE); // Non-FPSCR registers are not affected by FPEXC.EN AArch32.CheckAdvSIMDOrFPRegisterTraps(reg); case reg of when '0000' R[t] = FPSID; when '0101' R[t] = MVFR2; when '0110' R[t] = MVFR1; when '0111' R[t] = MVFR0; when '1000' R[t] = FPEXC; otherwise Unreachable(); // Dealt with above or in encoding-specific pseudocode
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.