VMUL (by scalar)

Vector Multiply multiplies each element in a vector by a scalar, and places the results in a second vector.

For more information about scalars see Advanced SIMD scalars.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
1111001Q1D!= 11VnVd100FN1M0Vm
size

64-bit SIMD vector (Q == 0)

VMUL{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm>[<index>]

128-bit SIMD vector (Q == 1)

VMUL{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Dm>[<index>]

if size == '11' then SEE "Related encodings"; if size == '00' || (F == '1' && size == '01' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED; constant unsigned = FALSE; // "Don't care" value: TRUE produces same functionality constant floating_point = (F == '1'); constant long_destination = FALSE; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant regs = if Q == '0' then 1 else 2; constant integer esize = 8 << UInt(size); constant integer elements = 64 DIV esize; integer m; integer index; if size == '01' then m = UInt(Vm<2:0>); index = UInt(M:Vm<3>); if size == '10' then m = UInt(Vm); index = UInt(M);

T1

15141312111098765432101514131211109876543210
111Q11111D!= 11VnVd100FN1M0Vm
size

64-bit SIMD vector (Q == 0)

VMUL{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm>[<index>]

128-bit SIMD vector (Q == 1)

VMUL{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Dm>[<index>]

if size == '11' then SEE "Related encodings"; if F == '1' && size == '01' && InITBlock() then UNPREDICTABLE; if size == '00' || (F == '1' && size == '01' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED; constant unsigned = FALSE; // "Don't care" value: TRUE produces same functionality constant floating_point = (F == '1'); constant long_destination = FALSE; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant regs = if Q == '0' then 1 else 2; constant integer esize = 8 << UInt(size); constant integer elements = 64 DIV esize; integer m; integer index; if size == '01' then m = UInt(Vm<2:0>); index = UInt(M:Vm<3>); if size == '10' then m = UInt(Vm); index = UInt(M);

CONSTRAINED UNPREDICTABLE behavior

If F == '1' && size == '01' && InITBlock(), then one of the following behaviors must occur:

Related encodings: See Advanced SIMD data-processing for the T32 instruction set, or Advanced SIMD data-processing for the A32 instruction set.

Assembler Symbols

<c>

For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional.

For encoding T1: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<dt>

Is the data type for the scalar and the elements of the operand vector, encoded in F:size:

F size <dt>
0 01 I16
0 10 I32
1 01 F16
1 10 F32
<Qd>

Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qn>

Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>

Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>

Is the 64-bit name of the second SIMD&FP source register. When <dt> is I16 or F16, this is encoded in the "Vm<2:0>" field. Otherwise it is encoded in the "Vm" field.

<index>

Is the element index. When <dt> is I16 or F16, this is in the range 0 to 3 and is encoded in the "M:Vm<3>" field. Otherwise it is in the range 0 to 1 and is encoded in the "M" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); constant FPCR_Type fpcr = StandardFPCR(); constant op2 = Elem[Din[m],index,esize]; constant op2val = Int(op2, unsigned); for r = 0 to regs-1 for e = 0 to elements-1 constant op1 = Elem[Din[n+r],e,esize]; constant op1val = Int(op1, unsigned); if floating_point then Elem[D[d+r],e,esize] = FPMul(op1, op2, fpcr); else if long_destination then Elem[Q[d>>1],e,2*esize] = (op1val*op2val)<2*esize-1:0>; else Elem[D[d+r],e,esize] = (op1val*op2val)<esize-1:0>;


Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05

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