Vector Multiply Long multiplies corresponding elements in two vectors. The destination vector elements are twice as long as the elements that are multiplied.
For information about multiplying polynomials see Polynomial arithmetic over {0, 1}.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | U | 1 | D | != 11 | Vn | Vd | 1 | 1 | op | 0 | N | 0 | M | 0 | Vm | ||||||||||
| size | |||||||||||||||||||||||||||||||
if size == '11' then SEE "Related encodings"; if op == '1' && (U == '1' || size == '01') then UNDEFINED; if op == '1' && size =='10' && !IsFeatureImplemented(FEAT_PMULL) then UNDEFINED; if Vd<0> == '1' then UNDEFINED; constant unsigned = (U == '1'); constant polynomial = (op == '1'); constant long_destination = TRUE; constant integer esize = if polynomial && size == '10' then 64 else 8 << UInt(size); constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm); constant elements = 64 DIV esize; constant regs = 1;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | U | 1 | 1 | 1 | 1 | 1 | D | != 11 | Vn | Vd | 1 | 1 | op | 0 | N | 0 | M | 0 | Vm | ||||||||||
| size | |||||||||||||||||||||||||||||||
if size == '11' then SEE "Related encodings"; if op == '1' && (U == '1' || size == '01') then UNDEFINED; if op == '1' && size == '10' && InITBlock() then UNPREDICTABLE; if op == '1' && size == '10' && !IsFeatureImplemented(FEAT_PMULL) then UNPREDICTABLE; if Vd<0> == '1' then UNDEFINED; constant unsigned = (U == '1'); constant polynomial = (op == '1'); constant long_destination = TRUE; constant integer esize = if polynomial && size == '10' then 64 else 8 << UInt(size); constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm); constant elements = 64 DIV esize; constant regs = 1;
If op == '1' && size == '10' && InITBlock(), then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
Related encodings: See Advanced SIMD data-processing for the T32 instruction set, or Advanced SIMD data-processing for the A32 instruction set.
| <c> |
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. |
|
For encoding T1: see Standard assembler syntax fields. |
| <q> |
| <dt> |
Is the data type for the elements of the operands,
encoded in
|
| <Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
| <Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
| <Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); for r = 0 to regs-1 for e = 0 to elements-1 constant op1 = Elem[Din[n+r],e,esize]; constant op1val = Int(op1, unsigned); constant op2 = Elem[Din[m+r],e,esize]; constant op2val = Int(op2, unsigned); bits(2 * esize) product; if polynomial then product = PolynomialMult(op1,op2); else product = (op1val*op2val)<2*esize-1:0>; if long_destination then Elem[Q[d>>1],e,2*esize] = product; else Elem[D[d+r],e,esize] = product<esize-1:0>;
If CPSR.DIT is 1 and this instruction passes its condition execution check:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.