Vector Negate Multiply multiplies together two floating-point register values, and writes the negation of the result to the destination register.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 1 | 1 | 1 | 0 | 0 | D | 1 | 0 | Vn | Vd | 1 | 0 | size | N | 1 | M | 0 | Vm | |||||||||||||
| cond | |||||||||||||||||||||||||||||||
if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; if size == '01' && !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; if size == '01' && cond != '1110' then UNPREDICTABLE; constant vtype = VFPNegMul_VNMUL; integer esize; integer d; integer n; integer m; case size of when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);
If size == '01' && cond != '1110', then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | D | 1 | 0 | Vn | Vd | 1 | 0 | size | N | 1 | M | 0 | Vm | ||||||||||
if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; if size == '01' && !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; if size == '01' && InITBlock() then UNPREDICTABLE; constant vtype = VFPNegMul_VNMUL; integer esize; integer d; integer n; integer m; case size of when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);
If size == '01' && InITBlock(), then one of the following behaviors must occur:
| <c> |
| <q> |
| <Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
| <Sn> |
Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field. |
| <Sm> |
Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field. |
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
| <Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
| <Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); constant FPCR_Type fpcr = EffectiveFPCR(); case esize of when 16 constant product16 = FPMul(H[n], H[m], fpcr); case vtype of when VFPNegMul_VNMLA H[d] = FPAdd(FPNeg(H[d], fpcr), FPNeg(product16, fpcr), fpcr); when VFPNegMul_VNMLS H[d] = FPAdd(FPNeg(H[d], fpcr), product16, fpcr); when VFPNegMul_VNMUL H[d] = FPNeg(product16, fpcr); when 32 constant product32 = FPMul(S[n], S[m], fpcr); case vtype of when VFPNegMul_VNMLA S[d] = FPAdd(FPNeg(S[d], fpcr), FPNeg(product32, fpcr), fpcr); when VFPNegMul_VNMLS S[d] = FPAdd(FPNeg(S[d], fpcr), product32, fpcr); when VFPNegMul_VNMUL S[d] = FPNeg(product32, fpcr); when 64 constant product64 = FPMul(D[n], D[m], fpcr); case vtype of when VFPNegMul_VNMLA D[d] = FPAdd(FPNeg(D[d], fpcr), FPNeg(product64, fpcr), fpcr); when VFPNegMul_VNMLS D[d] = FPAdd(FPNeg(D[d], fpcr), product64, fpcr); when VFPNegMul_VNMUL D[d] = FPNeg(product64, fpcr);
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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