Vector Pairwise Minimum compares adjacent pairs of elements in two doubleword vectors, and copies the smaller of each pair into the corresponding element in the destination doubleword vector.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | D | 1 | sz | Vn | Vd | 1 | 1 | 1 | 1 | N | 0 | M | 0 | Vm | |||||||||
| op | |||||||||||||||||||||||||||||||
if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; constant maximum = (op == '0'); constant integer esize = 32 >> UInt(sz); constant integer elements = 64 DIV esize; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | D | 1 | sz | Vn | Vd | 1 | 1 | 1 | 1 | N | 0 | M | 0 | Vm | |||||||||
| op | |||||||||||||||||||||||||||||||
if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; if sz == '1' && InITBlock() then UNPREDICTABLE; constant maximum = (op == '0'); constant integer esize = 32 >> UInt(sz); constant integer elements = 64 DIV esize; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm);
If sz == '1' && InITBlock(), then one of the following behaviors must occur:
| <c> |
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. |
|
For encoding T1: see Standard assembler syntax fields. |
| <q> |
| <dt> |
Is the data type for the elements of the vectors,
encoded in
|
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
| <Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
| <Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); bits(64) dest; constant FPCR_Type fpcr = StandardFPCR(); constant h = elements DIV 2; for e = 0 to h-1 op1 = Elem[D[n],2*e,esize]; op2 = Elem[D[n],2*e+1,esize]; Elem[dest,e,esize] = (if maximum then FPMax(op1,op2,fpcr) else FPMin(op1,op2,fpcr)); op1 = Elem[D[m],2*e,esize]; op2 = Elem[D[m],2*e+1,esize]; Elem[dest,e+h,esize] = (if maximum then FPMax(op1,op2,fpcr) else FPMin(op1,op2,fpcr)); D[d] = dest;
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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