VQDMLAL -- AArch32

Vector Saturating Doubling Multiply Accumulate Long multiplies corresponding elements in two doubleword vectors, doubles the products, and accumulates the results into the elements of a quadword vector.

The second operand can be a scalar instead of a vector. For more information about scalars see Advanced SIMD scalars.

If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .

if size == '11' then SEE "Related encodings"; if size == '00' || Vd<0> == '1' then UNDEFINED; constant add = (op == '0'); constant scalar_form = FALSE; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm); constant integer esize = 8 << UInt(size); constant elements = 64 DIV esize; constant integer index = integer UNKNOWN;

if size == '11' then SEE "Related encodings"; if size == '00' || Vd<0> == '1' then UNDEFINED; constant add = (op == '0'); constant scalar_form = TRUE; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant integer esize = 8 << UInt(size); constant integer elements = 64 DIV esize; integer m; integer index; if size == '01' then m = UInt(Vm<2:0>); index = UInt(M:Vm<3>); if size == '10' then m = UInt(Vm); index = UInt(M);

Assembler Symbols

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); integer op2; if scalar_form then op2 = SInt(Elem[Din[m],index,esize]); for e = 0 to elements-1 if !scalar_form then op2 = SInt(Elem[Din[m],e,esize]); constant op1 = SInt(Elem[Din[n],e,esize]); // The following only saturates if both op1 and op2 equal -(2^(esize-1)) constant (product, sat1) = SignedSatQ(2*op1*op2, 2*esize); integer result; if add then result = SInt(Elem[Qin[d>>1],e,2*esize]) + SInt(product); else result = SInt(Elem[Qin[d>>1],e,2*esize]) - SInt(product); boolean sat2; (Elem[Q[d>>1],e,2*esize], sat2) = SignedSatQ(result, 2*esize); if sat1 || sat2 then FPSCR.QC = '1';

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	0	1	0	1	D	!= 11		Vn				Vd				1	0	0	1	N	0	M	0	Vm
										size												op

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	0	1	0	1	D	!= 11		Vn				Vd				0	0	1	1	N	1	M	0	Vm
										size											op

<c>	For encoding A1 and A2: see Standard assembler syntax fields. This encoding must be unconditional.
	For encoding T1 and T2: see Standard assembler syntax fields.

<Dm>	For encoding A1 and T1: is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
	For encoding A2 and T2: is the 64-bit name of the second SIMD&FP source register, encoded in the "Vm<2:0>" field when <dt> is S16, otherwise the "Vm" field.