Vector Saturating Rounding Doubling Multiply Returning High Half multiplies corresponding elements in two vectors, doubles the results, and places the most significant half of the final results in the destination vector. The results are rounded. For truncated results see VQDMULH.
The second operand can be a scalar instead of a vector. For more information about scalars see Advanced SIMD scalars.
If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | D | size | Vn | Vd | 1 | 0 | 1 | 1 | N | Q | M | 0 | Vm | ||||||||||
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED; if size == '00' || size == '11' then UNDEFINED; constant scalar_form = FALSE; constant esize = 8 << UInt(size); constant elements = 64 DIV esize; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm); constant regs = if Q == '0' then 1 else 2; constant integer index = integer UNKNOWN;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | Q | 1 | D | != 11 | Vn | Vd | 1 | 1 | 0 | 1 | N | 1 | M | 0 | Vm | ||||||||||
| size | |||||||||||||||||||||||||||||||
if size == '11' then SEE "Related encodings"; if size == '00' then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED; constant scalar_form = TRUE; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant regs = if Q == '0' then 1 else 2; constant integer esize = 8 << UInt(size); constant integer elements = 64 DIV esize; integer m; integer index; if size == '01' then m = UInt(Vm<2:0>); index = UInt(M:Vm<3>); if size == '10' then m = UInt(Vm); index = UInt(M);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | D | size | Vn | Vd | 1 | 0 | 1 | 1 | N | Q | M | 0 | Vm | ||||||||||
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED; if size == '00' || size == '11' then UNDEFINED; constant scalar_form = FALSE; constant esize = 8 << UInt(size); constant elements = 64 DIV esize; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm); constant regs = if Q == '0' then 1 else 2; constant integer index = integer UNKNOWN;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | Q | 1 | 1 | 1 | 1 | 1 | D | != 11 | Vn | Vd | 1 | 1 | 0 | 1 | N | 1 | M | 0 | Vm | ||||||||||
| size | |||||||||||||||||||||||||||||||
if size == '11' then SEE "Related encodings"; if size == '00' then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED; constant scalar_form = TRUE; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant regs = if Q == '0' then 1 else 2; constant integer esize = 8 << UInt(size); constant integer elements = 64 DIV esize; integer m; integer index; if size == '01' then m = UInt(Vm<2:0>); index = UInt(M:Vm<3>); if size == '10' then m = UInt(Vm); index = UInt(M);
Related encodings: See Advanced SIMD data-processing for the T32 instruction set, or Advanced SIMD data-processing for the A32 instruction set.
| <c> |
For encoding A1 and A2: see Standard assembler syntax fields. This encoding must be unconditional. |
|
For encoding T1 and T2: see Standard assembler syntax fields. |
| <q> |
| <dt> |
Is the data type for the elements of the operands,
encoded in
|
| <Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
| <Qn> |
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2. |
| <Qm> |
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. |
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
| <Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
| <Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); integer op2; constant boolean round = TRUE; if scalar_form then op2 = SInt(Elem[D[m],index,esize]); for r = 0 to regs-1 for e = 0 to elements-1 constant op1 = SInt(Elem[D[n+r],e,esize]); if !scalar_form then op2 = SInt(Elem[D[m+r],e,esize]); constant integer rdmulh = RShr(2*op1*op2, esize, round); constant (result, sat) = SignedSatQ(rdmulh, esize); Elem[D[d+r],e,esize] = result; if sat then FPSCR.QC = '1';
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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