VREV16

Vector Reverse in halfwords reverses the order of 8-bit elements in each halfword of the vector, and places the result in the corresponding destination vector.

There is no distinction between data types, other than size.

The following figure shows an example of the operation of VREV16 doubleword operation.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

if UInt(op)+UInt(size) >= 3 then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED; constant esize = 8 << UInt(size); integer container_size; case op of when '10' container_size = 16; when '01' container_size = 32; when '00' container_size = 64; constant integer containers = 64 DIV container_size; constant integer elements_per_container = container_size DIV esize; constant d = UInt(D:Vd); constant m = UInt(M:Vm); constant regs = if Q == '0' then 1 else 2;

T1

if UInt(op)+UInt(size) >= 3 then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED; constant esize = 8 << UInt(size); integer container_size; case op of when '10' container_size = 16; when '01' container_size = 32; when '00' container_size = 64; constant integer containers = 64 DIV container_size; constant integer elements_per_container = container_size DIV esize; constant d = UInt(D:Vd); constant m = UInt(M:Vm); constant regs = if Q == '0' then 1 else 2;