VRINTA (Advanced SIMD)

Vector Round floating-point to integer towards Nearest with Ties to Away rounds a vector of floating-point values to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

if op<2> != op<0> then SEE "Related encodings"; if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED; if (size == '01' && !IsFeatureImplemented(FEAT_FP16)) || size IN {'00', '11'} then UNDEFINED; // Rounding encoded differently from other VCVT and VRINT instructions constant rounding = FPDecodeRM(op<2>:NOT(op<1>)); constant exact = FALSE; constant integer esize = 8 << UInt(size); constant integer elements = 64 DIV esize; constant d = UInt(D:Vd); constant m = UInt(M:Vm); constant regs = if Q == '0' then 1 else 2;

T1

if op<2> != op<0> then SEE "Related encodings"; if InITBlock() then UNPREDICTABLE; if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED; if (size == '01' && !IsFeatureImplemented(FEAT_FP16)) || size IN {'00', '11'} then UNDEFINED; // Rounding encoded differently from other VCVT and VRINT instructions constant rounding = FPDecodeRM(op<2>:NOT(op<1>)); constant exact = FALSE; constant integer esize = 8 << UInt(size); constant integer elements = 64 DIV esize; constant d = UInt(D:Vd); constant m = UInt(M:Vm); constant regs = if Q == '0' then 1 else 2;

CONSTRAINED UNPREDICTABLE behavior

If InITBlock(), then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as if it passes the Condition code check.
• The instruction executes as NOP. This means it behaves as if it fails the Condition code check.

Assembler Symbols