VRINTN (floating-point) -- AArch32

VRINTN (floating-point)

Round floating-point to integer to Nearest rounds a floating-point value to an integral floating-point value of the same size using the Round to Nearest rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	1	1	0	1	D	1	1	1	0	0	1	Vd				1	0	!= 00		0	1	M	0	Vm
														RM								size

if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; constant rounding = FPDecodeRM(RM); constant exact = FALSE; integer esize; integer d; integer m; case size of when '01' esize = 16; d = UInt(Vd:D); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); m = UInt(M:Vm);

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	1	1	0	1	D	1	1	1	0	0	1	Vd				1	0	!= 00		0	1	M	0	Vm
														RM								size

Half-precision scalar (size == 01)
(FEAT_FP16)

VRINTN{<q>}.F16 <Sd>, <Sm>

Single-precision scalar (size == 10)

VRINTN{<q>}.F32 <Sd>, <Sm>

Double-precision scalar (size == 11)

VRINTN{<q>}.F64 <Dd>, <Dm>

if InITBlock() then UNPREDICTABLE; if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; constant rounding = FPDecodeRM(RM); constant exact = FALSE; integer esize; integer d; integer m; case size of when '01' esize = 16; d = UInt(Vd:D); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); m = UInt(M:Vm);

CONSTRAINED UNPREDICTABLE behavior

If InITBlock(), then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<q>	See Standard assembler syntax fields.

<Sd>	Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sm>	Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.

<Dd>	Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>	Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

Operation

EncodingSpecificOperations(); CheckVFPEnabled(TRUE); constant FPCR_Type fpcr = EffectiveFPCR(); case esize of when 16 H[d] = FPRoundInt(H[m], fpcr, rounding, exact); when 32 S[d] = FPRoundInt(S[m], fpcr, rounding, exact); when 64 D[d] = FPRoundInt(D[m], fpcr, rounding, exact);

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05