VRSHL

Vector Rounding Shift Left takes each element in a vector, shifts them by a value from the least significant byte of the corresponding element of a second vector, and places the results in the destination vector. If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see VSHL.

The first operand and result elements are the same data type, and can be any one of:

• 8-bit, 16-bit, 32-bit, or 64-bit signed integers.
• 8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.

The second operand is always a signed integer of the same size.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

if Q == '1' && (Vd<0> == '1' || Vm<0> == '1' || Vn<0> == '1') then UNDEFINED; constant unsigned = (U == '1'); constant integer esize = 8 << UInt(size); constant elements = 64 DIV esize; constant d = UInt(D:Vd); constant m = UInt(M:Vm); constant n = UInt(N:Vn); constant regs = if Q == '0' then 1 else 2;

T1

if Q == '1' && (Vd<0> == '1' || Vm<0> == '1' || Vn<0> == '1') then UNDEFINED; constant unsigned = (U == '1'); constant integer esize = 8 << UInt(size); constant elements = 64 DIV esize; constant d = UInt(D:Vd); constant m = UInt(M:Vm); constant n = UInt(N:Vn); constant regs = if Q == '0' then 1 else 2;