Vector Rounding Shift Right and Narrow takes each element in a vector, right shifts them by an immediate value, and places the rounded results in the destination vector. For truncated results, see VSHRN.
The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers. The destination elements are half the size of the source elements.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | D | imm6 | Vd | 1 | 0 | 0 | 0 | 0 | 1 | M | 1 | Vm | |||||||||||
if imm6 IN {'000xxx'} then SEE "Related encodings"; if Vm<0> == '1' then UNDEFINED; constant integer esize = 8 << HighestSetBit(imm6<5:3>); constant integer elements = 64 DIV esize; constant integer shift_amount = (esize << 1) - UInt(imm6); constant d = UInt(D:Vd); constant m = UInt(M:Vm);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | D | imm6 | Vd | 1 | 0 | 0 | 0 | 0 | 1 | M | 1 | Vm | |||||||||||
if imm6 IN {'000xxx'} then SEE "Related encodings"; if Vm<0> == '1' then UNDEFINED; constant integer esize = 8 << HighestSetBit(imm6<5:3>); constant integer elements = 64 DIV esize; constant integer shift_amount = (esize << 1) - UInt(imm6); constant d = UInt(D:Vd); constant m = UInt(M:Vm);
Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.
| <c> |
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. |
|
For encoding T1: see Standard assembler syntax fields. |
| <q> |
| <size> |
Is the data size for the elements of the vectors,
encoded in
|
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
| <Qm> |
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. |
| <imm> |
Is an immediate value, in the range 1 to <size>/2, encoded in the "imm6" field as <size>/2 - <imm>. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); constant boolean round = TRUE; for e = 0 to elements-1 constant result = RShr(UInt(Elem[Qin[m>>1],e,2*esize]), shift_amount, round); Elem[D[d],e,esize] = result<esize-1:0>;
If CPSR.DIT is 1 and this instruction passes its condition execution check:
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
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