VST1 (multiple single elements) -- AArch32

Store multiple single elements from one, two, three, or four registers stores elements to memory from one, two, three, or four registers, without interleaving. Every element of each register is stored. For details of the addressing mode, see Advanced SIMD addressing mode.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 , A2 , A3 and A4 ) and T32 ( T1 , T2 , T3 and T4 ) .

constant regs = 1; if align<1> == '1' then UNDEFINED; constant alignment = if align == '00' then 1 else 4 << UInt(align); constant ebytes = 1 << UInt(size); constant elements = 8 DIV ebytes; constant d = UInt(D:Vd); constant n = UInt(Rn); constant m = UInt(Rm); constant wback = (m != 15); constant register_index = (m != 15 && m != 13); if n == 15 then UNPREDICTABLE;

constant regs = 2; if align == '11' then UNDEFINED; constant alignment = if align == '00' then 1 else 4 << UInt(align); constant ebytes = 1 << UInt(size); constant elements = 8 DIV ebytes; constant d = UInt(D:Vd); constant n = UInt(Rn); constant m = UInt(Rm); constant wback = (m != 15); constant register_index = (m != 15 && m != 13); if n == 15 || d+regs > 32 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

constant regs = 3; if align<1> == '1' then UNDEFINED; constant alignment = if align == '00' then 1 else 4 << UInt(align); constant ebytes = 1 << UInt(size); constant elements = 8 DIV ebytes; constant d = UInt(D:Vd); constant n = UInt(Rn); constant m = UInt(Rm); constant wback = (m != 15); constant register_index = (m != 15 && m != 13); if n == 15 || d+regs > 32 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

constant regs = 4; constant alignment = if align == '00' then 1 else 4 << UInt(align); constant ebytes = 1 << UInt(size); constant elements = 8 DIV ebytes; constant d = UInt(D:Vd); constant n = UInt(Rn); constant m = UInt(Rm); constant wback = (m != 15); constant register_index = (m != 15 && m != 13); if n == 15 || d+regs > 32 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VST1 (multiple single elements).

Related encodings: See Advanced SIMD element or structure load/store for the T32 instruction set, or Advanced SIMD element or structure load/store for the A32 instruction set.

Assembler Symbols

<c>	For encoding A1, A2, A3 and A4: see Standard assembler syntax fields. This encoding must be unconditional.
	For encoding T1, T2, T3 and T4: see Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<size>

Is the data size, encoded in size:

size	<size>
00	8
01	16
10	32
11	64

<list>

Is a list containing the 64-bit names of the SIMD&FP registers.

The list must be one of:

{ <Dd> }: Single register. Selects the A1 and T1 encodings of the instruction.
{ <Dd>, <Dd+1> }: Two single-spaced registers. Selects the A2 and T2 encodings of the instruction.
{ <Dd>, <Dd+1>, <Dd+2> }: Three single-spaced registers. Selects the A3 and T3 encodings of the instruction.
{ <Dd>, <Dd+1>, <Dd+2>, <Dd+3> }: Four single-spaced registers. Selects the A4 and T4 encodings of the instruction.

The register <Dd> is encoded in the "D:Vd" field.

<Rn>	Is the general-purpose base register, encoded in the "Rn" field.

<align>

Is the optional alignment.

Whenever <align> is omitted, the standard alignment is used, see Unaligned data access, and is encoded in the "align" field as 0b00.

Whenever <align> is present, the permitted values are:

64: 64-bit alignment, encoded in the "align" field as 0b01.
128: 128-bit alignment, encoded in the "align" field as 0b10. Available only if <list> contains two or four registers.
256: 256-bit alignment, encoded in the "align" field as 0b11. Available only if <list> contains four registers.

: is the preferred separator before the <align> value, but the alignment can be specified as @<align>, see Advanced SIMD addressing mode.

<Rm>	Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); address = R[n]; constant boolean nontemporal = FALSE; constant boolean tagchecked = FALSE; constant AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_STORE, nontemporal, tagchecked); if !IsAligned(address, alignment) then AArch32.Abort(address, AlignmentFault(accdesc)); for r = 0 to regs-1 for e = 0 to elements-1 if ebytes != 8 then MemU[address,ebytes] = Elem[D[d+r],e,8*ebytes]; else if !IsAligned(address, ebytes) && AlignmentEnforced() then AArch32.Abort(address, AlignmentFault(accdesc)); constant bits(64) data = Elem[D[d+r],e,64]; if BigEndian(AccessType_ASIMD) then MemU[address,4] = data<63:32>; MemU[address+4,4] = data<31:0>; else MemU[address,4] = data<31:0>; MemU[address+4,4] = data<63:32>; address = address + ebytes; if wback then if register_index then R[n] = R[n] + R[m]; else R[n] = R[n] + 8*regs;

Operational information

If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05

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1	1	1	1	0	1	0	0	0	D	0	0	Rn				Vd				0	1	1	1	size		align		Rm