Store multiple 2-element structures from two or four registers stores multiple 2-element structures from two or four registers to memory, with interleaving. For more information, see Element and structure load/store instructions. Every element of each register is saved. For details of the addressing mode, see Advanced SIMD addressing mode.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | D | 0 | 0 | Rn | Vd | 1 | 0 | 0 | x | size | align | Rm | |||||||||||
| itype | |||||||||||||||||||||||||||||||
constant pairs = 1; if align == '11' then UNDEFINED; if size == '11' then UNDEFINED; constant inc = if itype == '1001' then 2 else 1; constant alignment = if align == '00' then 1 else 4 << UInt(align); constant ebytes = 1 << UInt(size); constant elements = 8 DIV ebytes; constant d = UInt(D:Vd); constant d2 = d + inc; constant n = UInt(Rn); constant m = UInt(Rm); constant wback = (m != 15); constant register_index = (m != 15 && m != 13); if n == 15 || d2+pairs > 32 then UNPREDICTABLE;
If d2+pairs > 32, then one of the following behaviors must occur:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | D | 0 | 0 | Rn | Vd | 0 | 0 | 1 | 1 | size | align | Rm | |||||||||||
constant pairs = 2; constant inc = 2; if size == '11' then UNDEFINED; constant alignment = if align == '00' then 1 else 4 << UInt(align); constant ebytes = 1 << UInt(size); constant elements = 8 DIV ebytes; constant d = UInt(D:Vd); constant d2 = d + inc; constant n = UInt(Rn); constant m = UInt(Rm); constant wback = (m != 15); constant register_index = (m != 15 && m != 13); if n == 15 || d2+pairs > 32 then UNPREDICTABLE;
If d2+pairs > 32, then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | D | 0 | 0 | Rn | Vd | 1 | 0 | 0 | x | size | align | Rm | |||||||||||
| itype | |||||||||||||||||||||||||||||||
constant pairs = 1; if align == '11' then UNDEFINED; if size == '11' then UNDEFINED; constant inc = if itype == '1001' then 2 else 1; constant alignment = if align == '00' then 1 else 4 << UInt(align); constant ebytes = 1 << UInt(size); constant elements = 8 DIV ebytes; constant d = UInt(D:Vd); constant d2 = d + inc; constant n = UInt(Rn); constant m = UInt(Rm); constant wback = (m != 15); constant register_index = (m != 15 && m != 13); if n == 15 || d2+pairs > 32 then UNPREDICTABLE;
If d2+pairs > 32, then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | D | 0 | 0 | Rn | Vd | 0 | 0 | 1 | 1 | size | align | Rm | |||||||||||
constant pairs = 2; constant inc = 2; if size == '11' then UNDEFINED; constant alignment = if align == '00' then 1 else 4 << UInt(align); constant ebytes = 1 << UInt(size); constant elements = 8 DIV ebytes; constant d = UInt(D:Vd); constant d2 = d + inc; constant n = UInt(Rn); constant m = UInt(Rm); constant wback = (m != 15); constant register_index = (m != 15 && m != 13); if n == 15 || d2+pairs > 32 then UNPREDICTABLE;
If d2+pairs > 32, then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VST2 (multiple 2-element structures).
Related encodings: See Advanced SIMD element or structure load/store for the T32 instruction set, or Advanced SIMD element or structure load/store for the A32 instruction set.
| <c> |
For encoding A1 and A2: see Standard assembler syntax fields. This encoding must be unconditional. |
|
For encoding T1 and T2: see Standard assembler syntax fields. |
| <q> |
| <size> |
Is the data size,
encoded in
|
| <Rn> |
Is the general-purpose base register, encoded in the "Rn" field. |
| <align> |
Is the optional alignment. Whenever <align> is omitted, the standard alignment is used, see Unaligned data access, and is encoded in the "align" field as 0b00. Whenever <align> is present, the permitted values are:
: is the preferred separator before the <align> value, but the alignment can be specified as @<align>, see Advanced SIMD addressing mode. |
| <Rm> |
Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field. |
For more information about the variants of this instruction, see Advanced SIMD addressing mode.
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); address = R[n]; constant boolean nontemporal = FALSE; constant boolean tagchecked = FALSE; constant AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_STORE, nontemporal, tagchecked); if !IsAligned(address, alignment) then AArch32.Abort(address, AlignmentFault(accdesc)); for r = 0 to pairs-1 for e = 0 to elements-1 MemU[address, ebytes] = Elem[D[d+r], e,8*ebytes]; MemU[address+ebytes,ebytes] = Elem[D[d2+r],e,8*ebytes]; address = address + 2*ebytes; if wback then if register_index then R[n] = R[n] + R[m]; else R[n] = R[n] + 16*pairs;
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.