VTBL, VTBX

Vector Table Lookup uses byte indexes in a control vector to look up byte values in a table and generate a new vector. Indexes out of range return 0.

Vector Table Extension works in the same way, except that indexes out of range leave the destination element unchanged.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
111100111D11VnVd10lenNopM0Vm

VTBL (op == 0)

VTBL{<c>}{<q>}.8 <Dd>, <list>, <Dm>

VTBX (op == 1)

VTBX{<c>}{<q>}.8 <Dd>, <list>, <Dm>

constant is_vtbl = (op == '0'); constant length = UInt(len)+1; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm); if n+length > 32 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If n + length > 32, then one of the following behaviors must occur:

T1

15141312111098765432101514131211109876543210
111111111D11VnVd10lenNopM0Vm

VTBL (op == 0)

VTBL{<c>}{<q>}.8 <Dd>, <list>, <Dm>

VTBX (op == 1)

VTBX{<c>}{<q>}.8 <Dd>, <list>, <Dm>

constant is_vtbl = (op == '0'); constant length = UInt(len)+1; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm); if n+length > 32 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If n + length > 32, then one of the following behaviors must occur:

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional.

For encoding T1: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<list>

The vectors containing the table. It must be one of:

{<Dn>}
Encoded as len = 0b00.
{<Dn>, <Dn+1>}
Encoded as len = 0b01.
{<Dn>, <Dn+1>, <Dn+2>}
Encoded as len = 0b10.
{<Dn>, <Dn+1>, <Dn+2>, <Dn+3>}
Encoded as len = 0b11.
<Dm>

Is the 64-bit name of the SIMD&FP source register holding the indices, encoded in the "M:Vm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); // Create 256-bit = 32-byte table variable, with zeros in entries that will not be used. constant table3 = if length == 4 then D[n+3] else Zeros(64); constant table2 = if length >= 3 then D[n+2] else Zeros(64); constant table1 = if length >= 2 then D[n+1] else Zeros(64); constant table = table3 : table2 : table1 : D[n]; for i = 0 to 7 constant index = UInt(Elem[D[m],i,8]); if index < 8*length then Elem[D[d],i,8] = Elem[table,index,8]; else if is_vtbl then Elem[D[d],i,8] = Zeros(8); // else Elem[D[d],i,8] unchanged

Operational information

If CPSR.DIT is 1 and this instruction passes its condition execution check:


Internal version only: isa v01_31, pseudocode v2024-03_rel ; Build timestamp: 2024-03-25T10:05

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