ASR (register) -- AArch32

Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .

Encoding for the Not flag setting variant

ASR{<c>}{<q>} {<Rd>,} <Rm>, <Rs>

is equivalent to

MOV{<c>}{<q>} <Rd>, <Rm>, ASR <Rs>

and is always the preferred disassembly.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	0	0	0	0	1	0	0	Rs	Rdm
	op

Encoding for the Arithmetic shift right variant

ASR <c>{<q>} {<Rdm>,} <Rdm>, <Rs> // (Inside IT block)

is equivalent to

MOV <c>{<q>} <Rdm>, <Rdm>, ASR <Rs>

and is the preferred disassembly when InITBlock().

Encoding for the Not flag setting variant

ASR <c>.W {<Rd>,} <Rm>, <Rs> // (Inside IT block, and <Rd>, <Rm>, <shift>, <Rs> can be represented in T1)

ASR{<c>}{<q>} {<Rd>,} <Rm>, <Rs>

is equivalent to

MOV{<c>}{<q>} <Rd>, <Rm>, ASR <Rs>

and is always the preferred disassembly.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rdm>

Is the first general-purpose source register and the destination register, encoded in the "Rdm" field.

<Rd>	Is the general-purpose destination register, encoded in the "Rd" field.

<Rm>	Is the first general-purpose source register, encoded in the "Rm" field.

<Rs>	Is the second general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.

Operation

The description of MOV, MOVS (register-shifted register) gives the operational pseudocode for this instruction.

Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	0	0	1	1	0	1	0	(0)	(0)	(0)	(0)	Rd				Rs				0	1	0	1	Rm
cond											S														stype