BLX (register)

Branch with Link and Exchange (register) calls a subroutine at an address specified in the register, and if necessary changes to the instruction set indicated by bit[0] of the register value. If the value in bit[0] is 0, the instruction set after the branch will be A32. If the value in bit[0] is 1, the instruction set after the branch will be T32.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111100010010(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)0011Rm
cond

Encoding for the A1 variant

BLX{<c>}{<q>} <Rm>

Decode for this encoding

constant m = UInt(Rm); if m == 15 then UNPREDICTABLE;

T1

1514131211109876543210
010001111Rm(0)(0)(0)

Encoding for the T1 variant

BLX{<c>}{<q>} <Rm>

Decode for this encoding

constant m = UInt(Rm); if m == 15 then UNPREDICTABLE; if InITBlock() && !LastInITBlock() then UNPREDICTABLE;

For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rm>

Is the general-purpose register holding the address to be branched to, encoded in the "Rm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); constant target = R[m]; bits(32) next_instr_addr; if CurrentInstrSet() == InstrSet_A32 then next_instr_addr = PC32 - 4; LR = next_instr_addr; else next_instr_addr = PC32 - 2; LR = next_instr_addr<31:1> : '1'; BXWritePC(target, BranchType_INDCALL);


Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54

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