Branch and Exchange, previously Branch and Exchange Jazelle.
BXJ behaves as a BX instruction, see BX. This means it causes a branch to an address and instruction set specified by a register.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | (1) | (1) | (1) | (1) | (1) | (1) | (1) | (1) | (1) | (1) | (1) | (1) | 0 | 0 | 1 | 0 | Rm | ||||||
| cond | |||||||||||||||||||||||||||||||
constant m = UInt(Rm); if m == 15 then UNPREDICTABLE;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | Rm | 1 | 0 | (0) | 0 | (1) | (1) | (1) | (1) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | (0) | |||
constant m = UInt(Rm); // Armv8-A removes UNPREDICTABLE for R13 if m == 15 then UNPREDICTABLE; if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rm> |
Is the general-purpose register holding the address to be branched to, encoded in the "Rm" field. |
if ConditionPassed() then EncodingSpecificOperations(); BXWritePC(R[m], BranchType_INDIR);
Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54
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