MOV, MOVS (register)

Move (register) copies a value from a register to the destination register.

If the destination register is not the PC, the MOVS variant of the instruction updates the condition flags based on the result.

The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:

• The MOV variant of the instruction is a branch. In the T32 instruction set (encoding T1) this is a simple branch, and in the A32 instruction set it is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
• The MOVS variant of the instruction performs an exception return without the use of the stack. In this case:
  • The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.
  • The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32 state.
  • The instruction is undefined in Hyp mode.
  • The instruction is constrained unpredictable in User mode and System mode.

This instruction is used by the aliases ASRS (immediate), ASR (immediate), LSLS (immediate), LSL (immediate), LSRS (immediate), LSR (immediate), RORS (immediate), ROR (immediate), RRXS, and RRX.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 and T3 ) .

A1

Decode for all variants of this encoding

constant d = UInt(Rd); constant m = UInt(Rm); constant setflags = (S == '1'); constant (shift_t, shift_n) = DecodeImmShift(stype, imm5);

T1

Decode for this encoding

constant d = UInt(D:Rd); constant m = UInt(Rm); constant setflags = FALSE; constant (shift_t, shift_n) = (SRType_LSL, 0); if d == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;

T2

Decode for this encoding

constant d = UInt(Rd); constant m = UInt(Rm); constant setflags = !InITBlock(); constant (shift_t, shift_n) = DecodeImmShift(op, imm5); if op == '00' && imm5 == '00000' && InITBlock() then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If op == '00' && imm5 == '00000' && InITBlock(), then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as if it passed its condition code check.
• The instruction executes as NOP, as if it failed its condition code check.
• The instruction executes as MOV Rd, Rm.

T3

Decode for all variants of this encoding

constant d = UInt(Rd); constant m = UInt(Rm); constant setflags = (S == '1'); constant (shift_t, shift_n) = DecodeImmShift(stype, imm3:imm2); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || m == 15 then UNPREDICTABLE;

Assembler Symbols