MVN, MVNS (register-shifted register)

Bitwise NOT (register-shifted register) writes the bitwise inverse of a register-shifted register value to the destination register. It can optionally update the condition flags based on the result.

A1

313029282726252423222120191817161514131211109876543210
!= 11110001111S(0)(0)(0)(0)RdRs0stype1Rm
cond

Encoding for the Flag setting variant

Applies when (S == 1)

MVNS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs>

Encoding for the Not flag setting variant

Applies when (S == 0)

MVN{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs>

Decode for all variants of this encoding

constant d = UInt(Rd); constant m = UInt(Rm); constant s = UInt(Rs); constant setflags = (S == '1'); constant shift_t = DecodeRegShift(stype); if d == 15 || m == 15 || s == 15 then UNPREDICTABLE;

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field.

<Rm>

Is the general-purpose source register, encoded in the "Rm" field.

<shift>

Is the type of shift to be applied to the second source register, encoded in stype:

stype <shift>
00 LSL
01 LSR
10 ASR
11 ROR
<Rs>

Is the general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); constant shift_n = UInt(R[s]<7:0>); constant (shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C); constant result = NOT(shifted); R[d] = result; if setflags then PSTATE.N = result<31>; PSTATE.Z = IsZeroBit(result); PSTATE.C = carry; // PSTATE.V unchanged


Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54

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