Push Single Register to Stack stores a single general-purpose register to the stack, storing to the 32-bit word below the address in SP, and updates SP to point to the start of the stored data.
This is an alias of STR (immediate). This means:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T4 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | Rt | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | ||||||
| cond | P | U | W | Rn | imm12 | ||||||||||||||||||||||||||
PUSH{<c>}{<q>} <single_register_list>
is equivalent to
STR{<c>}{<q>} <Rt>, [SP, #-4]!
and is always the preferred disassembly.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | Rt | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | |||
| Rn | P | U | W | imm8 | |||||||||||||||||||||||||||
PUSH{<c>}{<q>} <single_register_list> // (Standard syntax)
is equivalent to
STR{<c>}{<q>} <Rt>, [SP, #-4]!
and is always the preferred disassembly.
| <c> |
| <q> |
| <single_register_list> |
Is the general-purpose register <Rt> to be stored surrounded by { and }. |
The description of STR (immediate) gives the operational pseudocode for this instruction.
Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54
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