Signed Multiply Subtract Dual performs two signed 16 x 16-bit multiplications. It subtracts one of the products from the other, and writes the result to the destination register.
Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication.
Overflow cannot occur.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | Rd | 1 | 1 | 1 | 1 | Rm | 0 | 1 | M | 1 | Rn | ||||||||||||
| cond | |||||||||||||||||||||||||||||||
constant d = UInt(Rd); constant n = UInt(Rn); constant m = UInt(Rm); constant m_swap = (M == '1'); if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | Rn | 1 | 1 | 1 | 1 | Rd | 0 | 0 | 0 | M | Rm | |||||||||
constant d = UInt(Rd); constant n = UInt(Rn); constant m = UInt(Rm); constant m_swap = (M == '1'); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rd> |
Is the general-purpose destination register, encoded in the "Rd" field. |
| <Rn> |
Is the first general-purpose source register, encoded in the "Rn" field. |
| <Rm> |
Is the second general-purpose source register, encoded in the "Rm" field. |
if ConditionPassed() then EncodingSpecificOperations(); constant operand2 = if m_swap then ROR(R[m],16) else R[m]; constant product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>); constant product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>); constant result = product1 - product2; R[d] = result<31:0>; // Signed overflow cannot occur
Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54
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