In an EL1 mode other than System mode, Store Multiple (User registers) stores multiple User mode registers to consecutive memory locations using an address from a base register. The PE reads the base register value normally, using the current mode to determine the correct Banked version of the register. This instruction cannot writeback to the base register.
Store Multiple (User registers) is undefined in Hyp mode, and constrained unpredictable in User or System modes.
Armv8.2 permits the deprecation of some Store Multiple ordering behaviors in AArch32 state, for more information see FEAT_LSMAOC.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 1 | 0 | 0 | P | U | 1 | (0) | 0 | Rn | register_list | |||||||||||||||||||||
| cond | |||||||||||||||||||||||||||||||
constant n = UInt(Rn); constant registers = register_list; constant increment = (U == '1'); constant wordhigher = (P == U); if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
If BitCount(registers) < 1, then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rn> |
Is the general-purpose base register, encoded in the "Rn" field. |
| <registers> |
Is a list of one or more registers, separated by commas and surrounded by { and }. It specifies the set of registers to be stored by the STM instruction. The registers are stored with the lowest-numbered register to the lowest memory address, through to the highest-numbered register to the highest memory address. See also Encoding of lists of general-purpose registers and the PC. |
if ConditionPassed() then EncodingSpecificOperations(); if PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.M IN {M32_User,M32_System} then UNPREDICTABLE; else constant length = 4*BitCount(registers); address = if increment then R[n] else R[n]-length; if wordhigher then address = address+4; for i = 0 to 14 if registers<i> == '1' then // Store User mode register MemS[address,4] = Rmode[i, M32_User]; address = address + 4; if registers<15> == '1' then MemS[address,4] = PCStoreValue();
If PSTATE.M IN {M32_User,M32_System}, then one of the following behaviors must occur:
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54
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