TSB

Trace Synchronization Barrier. This instruction is a barrier that synchronizes the trace operations of instructions, see Trace Synchronization Barrier (TSB).

If FEAT_TRF is not implemented, this instruction executes as a NOP.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1
(FEAT_TRF)

313029282726252423222120191817161514131211109876543210
!= 1111001100100000(1)(1)(1)(1)(0)(0)(0)(0)00010010
cond

Encoding for the A1 variant

TSB{<c>}{<q>} CSYNC

Decode for this encoding

if !IsFeatureImplemented(FEAT_TRF) then ExecuteAsNOP(); if cond != '1110' then UNPREDICTABLE; // TSB must be encoded with AL condition

CONSTRAINED UNPREDICTABLE behavior

If cond != '1110', then one of the following behaviors must occur:

T1
(FEAT_TRF)

15141312111098765432101514131211109876543210
111100111010(1)(1)(1)(1)10(0)0(0)00000010010

Encoding for the T1 variant

TSB{<c>}{<q>} CSYNC

Decode for this encoding

if !IsFeatureImplemented(FEAT_TRF) then ExecuteAsNOP(); if InITBlock() then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If InITBlock(), then one of the following behaviors must occur:

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

Operation

if ConditionPassed() then EncodingSpecificOperations(); TraceSynchronizationBarrier();


Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.