UMULL, UMULLS

Unsigned Multiply Long multiplies two 32-bit unsigned values to produce a 64-bit result.

In A32 instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many implementations.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 11110000100SRdHiRdLoRm1001Rn
cond

Encoding for the Flag setting variant

Applies when (S == 1)

UMULLS{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>

Encoding for the Not flag setting variant

Applies when (S == 0)

UMULL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>

Decode for all variants of this encoding

constant dLo = UInt(RdLo); constant dHi = UInt(RdHi); constant n = UInt(Rn); constant m = UInt(Rm); constant setflags = (S == '1'); if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; if dHi == dLo then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If dHi == dLo, then one of the following behaviors must occur:

T1

15141312111098765432101514131211109876543210
111110111010RnRdLoRdHi0000Rm

Encoding for the T1 variant

UMULL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>

Decode for this encoding

constant dLo = UInt(RdLo); constant dHi = UInt(RdHi); constant n = UInt(Rn); constant m = UInt(Rm); constant setflags = FALSE; if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 if dHi == dLo then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If dHi == dLo, then one of the following behaviors must occur:

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<RdLo>

Is the general-purpose destination register for the lower 32 bits of the result, encoded in the "RdLo" field.

<RdHi>

Is the general-purpose destination register for the upper 32 bits of the result, encoded in the "RdHi" field.

<Rn>

Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.

<Rm>

Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); constant result = UInt(R[n]) * UInt(R[m]); R[dHi] = result<63:32>; R[dLo] = result<31:0>; if setflags then PSTATE.N = result<63>; PSTATE.Z = IsZeroBit(result<63:0>); // PSTATE.C, PSTATE.V unchanged

Operational information

If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:


Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54

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