Vector Absolute Compare Less Than takes the absolute value of each element in a vector, and compares it with the absolute value of the corresponding element of a second vector. If the first is less than the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.
This is a pseudo-instruction of VACGT. This means:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | D | 1 | sz | Vn | Vd | 1 | 1 | 1 | 0 | N | Q | M | 1 | Vm | |||||||||
| op | |||||||||||||||||||||||||||||||
VACLT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
is equivalent to
VACLT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
is equivalent to
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | D | 1 | sz | Vn | Vd | 1 | 1 | 1 | 0 | N | Q | M | 1 | Vm | |||||||||
| op | |||||||||||||||||||||||||||||||
VACLT{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>
is equivalent to
VACLT{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
is equivalent to
| <Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. |
| <Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
| <Qm> |
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. |
| <Qn> |
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2. |
| <c> |
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. |
|
For encoding T1: see Standard assembler syntax fields. |
| <q> |
| <dt> |
Is the data type for the elements of the vectors,
encoded in
|
| <Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
The description of VACGT gives the operational pseudocode for this instruction.
The description of VACGT gives the operational pseudocode for this instruction.
Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54
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