Vector Convert between half-precision and single-precision converts each element in a vector from single-precision to half-precision floating-point, or from half-precision to single-precision, and places the results in a second vector.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | D | 1 | 1 | size | 1 | 0 | Vd | 0 | 1 | 1 | op | 0 | 0 | M | 0 | Vm | |||||||
if size != '01' then UNDEFINED; constant half_to_single = (op == '1'); if half_to_single && Vd<0> == '1' then UNDEFINED; if !half_to_single && Vm<0> == '1' then UNDEFINED; constant esize = 16; constant elements = 4; constant m = UInt(M:Vm); constant d = UInt(D:Vd);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | D | 1 | 1 | size | 1 | 0 | Vd | 0 | 1 | 1 | op | 0 | 0 | M | 0 | Vm | |||||||
if size != '01' then UNDEFINED; constant half_to_single = (op == '1'); if half_to_single && Vd<0> == '1' then UNDEFINED; if !half_to_single && Vm<0> == '1' then UNDEFINED; constant esize = 16; constant elements = 4; constant m = UInt(M:Vm); constant d = UInt(D:Vd);
| <c> |
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. |
|
For encoding T1: see Standard assembler syntax fields. |
| <q> |
| <Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
| <Dm> |
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field. |
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
| <Qm> |
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); constant FPCR_Type fpcr = StandardFPCR(); for e = 0 to elements-1 if half_to_single then Elem[Q[d>>1],e,32] = FPConvert(Elem[Din[m],e,16], fpcr, 32); else Elem[D[d],e,16] = FPConvert(Elem[Qin[m>>1],e,32], fpcr, 16);
Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.