Convert to or from a half-precision value in the bottom half of a single-precision register does one of the following:
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 0 | 1 | op | Vd | 1 | 0 | 1 | sz | 0 | 1 | M | 0 | Vm | |||||||||
| cond | T | ||||||||||||||||||||||||||||||
constant uses_double = (sz == '1'); constant convert_from_half = (op == '0'); constant integer lowbit = (if T == '1' then 16 else 0); constant integer d = if uses_double && convert_from_half then UInt(D:Vd) else UInt(Vd:D); constant integer m = if uses_double && !convert_from_half then UInt(M:Vm) else UInt(Vm:M);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 0 | 1 | op | Vd | 1 | 0 | 1 | sz | 0 | 1 | M | 0 | Vm | ||||||
| T | |||||||||||||||||||||||||||||||
constant uses_double = (sz == '1'); constant convert_from_half = (op == '0'); constant integer lowbit = (if T == '1' then 16 else 0); constant integer d = if uses_double && convert_from_half then UInt(D:Vd) else UInt(Vd:D); constant integer m = if uses_double && !convert_from_half then UInt(M:Vm) else UInt(Vm:M);
| <c> |
| <q> |
| <Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
| <Dm> |
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field. |
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
| <Sm> |
Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); bits(16) hp; constant FPCR_Type fpcr = EffectiveFPCR(); if convert_from_half then hp = S[m]<lowbit+15:lowbit>; if uses_double then D[d] = FPConvert(hp, fpcr, 64); else S[d] = FPConvert(hp, fpcr, 32); else if uses_double then hp = FPConvert(D[m], fpcr, 16); else hp = FPConvert(S[m], fpcr, 16); S[d]<lowbit+15:lowbit> = hp;
Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54
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