VFMSL (vector)

Vector Floating-point Multiply-Subtract Long from accumulator (vector). This instruction negates the values in the vector of one SIMD&FP register, multiplies these with the corresponding values in another vector, and accumulates the product to the corresponding vector element of the destination SIMD&FP register. The instruction does not round the result of the multiply before the accumulation.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1
(FEAT_FHM)

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_FHM) then UNDEFINED; if Q == '1' && Vd<0> == '1' then UNDEFINED; constant integer d = UInt(D:Vd); constant integer n = if Q == '1' then UInt(N:Vn) else UInt(Vn:N); constant integer m = if Q == '1' then UInt(M:Vm) else UInt(Vm:M); constant integer esize = 32; constant integer datasize = 32 << UInt(Q); constant boolean sub_op = S == '1'; constant integer regs = if Q == '0' then 1 else 2;

T1
(FEAT_FHM)

Decode for all variants of this encoding

if InITBlock() then UNPREDICTABLE; if !IsFeatureImplemented(FEAT_FHM) then UNDEFINED; if Q == '1' && Vd<0> == '1' then UNDEFINED; constant integer d = UInt(D:Vd); constant integer n = if Q == '1' then UInt(N:Vn) else UInt(Vn:N); constant integer m = if Q == '1' then UInt(M:Vm) else UInt(Vm:M); constant integer esize = 32; constant integer regs = 1 << UInt(Q); constant integer datasize = 32 << UInt(Q); constant boolean sub_op = S == '1';