Vector Floating-point Multiply-Subtract Long from accumulator (by scalar). This instruction multiplies the negated vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the product to the corresponding vector element of the destination SIMD&FP register. The instruction does not round the result of the multiply before the accumulation.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | D | 0 | 1 | Vn | Vd | 1 | 0 | 0 | 0 | N | Q | M | 1 | Vm | |||||||||
S |
if !IsFeatureImplemented(FEAT_FHM) then UNDEFINED; if Q == '1' && Vd<0> == '1' then UNDEFINED; constant integer d = UInt(D:Vd); constant integer n = if Q == '1' then UInt(N:Vn) else UInt(Vn:N); constant integer m = if Q == '1' then UInt(Vm<2:0>) else UInt(Vm<2:0>:M); constant integer index = if Q == '1' then UInt(M:Vm<3>) else UInt(Vm<3>); constant integer esize = 32; constant integer datasize = 32 << UInt(Q); constant boolean sub_op = S == '1'; constant integer regs = if Q == '0' then 1 else 2;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | D | 0 | 1 | Vn | Vd | 1 | 0 | 0 | 0 | N | Q | M | 1 | Vm | |||||||||
S |
if InITBlock() then UNPREDICTABLE; if !IsFeatureImplemented(FEAT_FHM) then UNDEFINED; if Q == '1' && Vd<0> == '1' then UNDEFINED; constant integer d = UInt(D:Vd); constant integer n = if Q == '1' then UInt(N:Vn) else UInt(Vn:N); constant integer m = if Q == '1' then UInt(Vm<2:0>) else UInt(Vm<2:0>:M); constant integer index = if Q == '1' then UInt(M:Vm<3>) else UInt(Vm<3>); constant integer esize = 32; constant integer datasize = 32 << UInt(Q); constant boolean sub_op = S == '1'; constant integer regs = if Q == '0' then 1 else 2;
<q> |
<Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
<Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
<Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "Vm<2:0>" field. |
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Sn> |
Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field. |
<Sm> |
Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm<2:0>:M" field. |
CheckAdvSIMDEnabled(); bits(datasize) operand1 ; bits(datasize) operand2 ; bits(64) operand3; bits(64) result; bits(esize DIV 2) element1; bits(esize DIV 2) element2; constant FPCR_Type fpcr = StandardFPCR(); if Q=='0' then operand1 = S[n]<datasize-1:0>; operand2 = S[m]<datasize-1:0>; else operand1 = D[n]<datasize-1:0>; operand2 = D[m]<datasize-1:0>; element2 = Elem[operand2, index, esize DIV 2]; for r = 0 to regs-1 operand3 = D[d+r]; for e = 0 to 1 element1 = Elem[operand1, 2*r+e, esize DIV 2]; if sub_op then element1 = FPNeg(element1, fpcr); Elem[result, e, esize] = FPMulAddH(Elem[operand3, e, esize], element1, element2, fpcr); D[d+r] = result;
Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54
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