VLD3 (single 3-element structure to all lanes) -- AArch32

VLD3 (single 3-element structure to all lanes)

Load single 3-element structure and replicate to all lanes of three registers loads one 3-element structure from memory into all lanes of three registers. For details of the addressing mode, see Advanced SIMD addressing mode.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	1	0	0	1	D	1	0	Rn				Vd				1	1	1	0	size		T	0	Rm
																											a

Decode for all variants of this encoding

if size == '11' || a == '1' then UNDEFINED; constant ebytes = 1 << UInt(size); constant inc = if T == '0' then 1 else 2; constant d = UInt(D:Vd); constant d2 = d + inc; constant d3 = d2 + inc; constant n = UInt(Rn); constant m = UInt(Rm); constant wback = (m != 15); constant register_index = (m != 15 && m != 13); if n == 15 || d3 > 31 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If d3 > 31, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
One or more of the SIMD and floating-point registers are unknown. If the instruction specifies writeback, the base register becomes unknown. This behavior does not affect any general-purpose registers.

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	0	1	1	D	1	0	Rn				Vd				1	1	1	0	size		T	0	Rm
																											a

Encoding for the Offset variant

Applies when (Rm == 1111)

VLD3{<c>}{<q>}.<size> <list>, [<Rn>]

Encoding for the Post-indexed variant

Applies when (Rm == 1101)

VLD3{<c>}{<q>}.<size> <list>, [<Rn>]!

Encoding for the Post-indexed variant

Applies when (Rm != 11x1)

VLD3{<c>}{<q>}.<size> <list>, [<Rn>], <Rm>

Decode for all variants of this encoding

CONSTRAINED UNPREDICTABLE behavior

If d3 > 31, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
One or more of the SIMD and floating-point registers are unknown. If the instruction specifies writeback, the base register becomes unknown. This behavior does not affect any general-purpose registers.

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VLD3 (single 3-element structure to all lanes).

Assembler Symbols

<c>	For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional.
	For encoding T1: see Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<size>

Is the data size, encoded in size:

size	<size>
00	8
01	16
10	32
11	RESERVED

<list>

Is a list containing the 64-bit names of three SIMD&FP registers.

The list must be one of:

{ <Dd>[], <Dd+1>[], <Dd+2>[] }: Single-spaced registers, encoded in the "T" field as 0.
{ <Dd>[], <Dd+2>[], <Dd+4>[] }: Double-spaced registers, encoded in the "T" field as 1.

The register <Dd> is encoded in the "D:Vd" field.

<Rn>	Is the general-purpose base register, encoded in the "Rn" field.

<Rm>	Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.

For more information about the variants of this instruction, see Advanced SIMD addressing mode.

Alignment

Standard alignment rules apply, see Alignment support.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); constant address = R[n]; constant integer esize = ebytes * 8; constant bits(esize) element1 = MemU[address, ebytes]; constant bits(esize) element2 = MemU[address+ebytes,ebytes]; constant bits(esize) element3 = MemU[address+2*ebytes,ebytes]; D[d] = Replicate(element1, 64 DIV esize); D[d2] = Replicate(element2, 64 DIV esize); D[d3] = Replicate(element3, 64 DIV esize); if wback then if register_index then R[n] = R[n] + R[m]; else R[n] = R[n] + 3*ebytes;

Operational information

If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54