Load SIMD&FP register (immediate) loads a single register from the Advanced SIMD and floating-point register file, using an address from a general-purpose register, with an optional offset.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 1 | 1 | 0 | 1 | U | D | 0 | 1 | != 1111 | Vd | 1 | 0 | size | imm8 | |||||||||||||||||
| cond | Rn | ||||||||||||||||||||||||||||||
if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; if size == '01' && cond != '1110' then UNPREDICTABLE; constant esize = 8 << UInt(size); constant add = (U == '1'); constant imm32 = if esize == 16 then ZeroExtend(imm8:'0', 32) else ZeroExtend(imm8:'00', 32); constant d = if size == '11' then UInt(D:Vd) else UInt(Vd:D); constant n = UInt(Rn);
If size == '01' && cond != '1110', then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | U | D | 0 | 1 | != 1111 | Vd | 1 | 0 | size | imm8 | ||||||||||||||
| Rn | |||||||||||||||||||||||||||||||
if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; if size == '01' && InITBlock() then UNPREDICTABLE; constant esize = 8 << UInt(size); constant add = (U == '1'); constant imm32 = if esize == 16 then ZeroExtend(imm8:'0', 32) else ZeroExtend(imm8:'00', 32); constant d = if size == '11' then UInt(D:Vd) else UInt(Vd:D); constant n = UInt(Rn);
If size == '01' && InITBlock(), then one of the following behaviors must occur:
| <c> |
| <q> |
| .64 |
Is an optional data size specifier for 64-bit memory accesses that can be used in the assembler source code, but is otherwise ignored. |
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
| .32 |
Is an optional data size specifier for 32-bit memory accesses that can be used in the assembler source code, but is otherwise ignored. |
| <Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
| <Rn> |
Is the general-purpose base register, encoded in the "Rn" field. |
| +/- |
Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
|
if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); constant base = if n == 15 then Align(PC32,4) else R[n]; constant address = if add then (base + imm32) else (base - imm32); case esize of when 16 H[d] = MemA[address,2]; when 32 S[d] = MemA[address,4]; when 64 constant word1 = MemA[address,4]; constant word2 = MemA[address+4,4]; // Combine the word-aligned words in the correct order for current endianness. D[d] = if BigEndian(AccessType_ASIMD) then word1:word2 else word2:word1;
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54
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