This instruction determines the floating point minimum number.
It handles NaNs in consistence with the IEEE754-2008 specification. It returns the numerical operand when one operand is numerical and the other is a quiet NaN, but otherwise the result is identical to floating-point VMIN.
This instruction is not conditional.
It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .
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| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | D | 1 | sz | Vn | Vd | 1 | 1 | 1 | 1 | N | Q | M | 1 | Vm | |||||||||
| op | |||||||||||||||||||||||||||||||
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED; if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; constant maximum = (op == '0'); constant advsimd = TRUE; constant integer esize = 32 >> UInt(sz); constant integer elements = 64 DIV esize; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm); constant regs = if Q == '0' then 1 else 2;
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| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | D | 0 | 0 | Vn | Vd | 1 | 0 | != 00 | N | 1 | M | 0 | Vm | ||||||||||
| size | op | ||||||||||||||||||||||||||||||
if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; constant advsimd = FALSE; constant maximum = (op == '0'); constant integer esize = 8 << UInt(size); constant integer d = if size == '11' then UInt(D:Vd) else UInt(Vd:D); constant integer n = if size == '11' then UInt(N:Vn) else UInt(Vn:N); constant integer m = if size == '11' then UInt(M:Vm) else UInt(Vm:M); constant integer regs = integer UNKNOWN; constant integer elements = integer UNKNOWN;
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| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | D | 1 | sz | Vn | Vd | 1 | 1 | 1 | 1 | N | Q | M | 1 | Vm | |||||||||
| op | |||||||||||||||||||||||||||||||
if InITBlock() then UNPREDICTABLE; if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED; if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; constant maximum = (op == '0'); constant advsimd = TRUE; constant integer esize = 32 >> UInt(sz); constant integer elements = 64 DIV esize; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm); constant regs = if Q == '0' then 1 else 2;
If InITBlock(), then one of the following behaviors must occur:
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| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | D | 0 | 0 | Vn | Vd | 1 | 0 | != 00 | N | 1 | M | 0 | Vm | ||||||||||
| size | op | ||||||||||||||||||||||||||||||
VMINNM{<q>}.F16 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)
VMINNM{<q>}.F32 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)
VMINNM{<q>}.F64 <Dd>, <Dn>, <Dm> // (Not permitted in IT block)
if InITBlock() then UNPREDICTABLE; if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; constant advsimd = FALSE; constant maximum = (op == '0'); constant integer esize = 8 << UInt(size); constant integer d = if size == '11' then UInt(D:Vd) else UInt(Vd:D); constant integer n = if size == '11' then UInt(N:Vn) else UInt(Vn:N); constant integer m = if size == '11' then UInt(M:Vm) else UInt(Vm:M); constant integer regs = integer UNKNOWN; constant integer elements = integer UNKNOWN;
If InITBlock(), then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <q> |
| <dt> |
Is the data type for the elements of the vectors,
encoded in
|
| <Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
| <Qn> |
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2. |
| <Qm> |
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. |
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
| <Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
| <Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. |
| <Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
| <Sn> |
Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field. |
| <Sm> |
Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field. |
EncodingSpecificOperations(); CheckAdvSIMDOrVFPEnabled(TRUE, advsimd); if advsimd then // Advanced SIMD instruction constant FPCR_Type fpcr = StandardFPCR(); for r = 0 to regs-1 for e = 0 to elements-1 constant op1 = Elem[D[n+r], e, esize]; constant op2 = Elem[D[m+r], e, esize]; if maximum then Elem[D[d+r], e, esize] = FPMaxNum(op1, op2, fpcr); else Elem[D[d+r], e, esize] = FPMinNum(op1, op2, fpcr); else // VFP instruction constant FPCR_Type fpcr = EffectiveFPCR(); case esize of when 16 if maximum then H[d] = FPMaxNum(H[n], H[m], fpcr); else H[d] = FPMinNum(H[n], H[m], fpcr); when 32 if maximum then S[d] = FPMaxNum(S[n], S[m], fpcr); else S[d] = FPMinNum(S[n], S[m], fpcr); when 64 if maximum then D[d] = FPMaxNum(D[n], D[m], fpcr); else D[d] = FPMinNum(D[n], D[m], fpcr);
Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54
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