VMOV (immediate) -- AArch32

VMOV (immediate)

Copy immediate value to a SIMD&FP register places an immediate constant into every element of the destination register.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 , A2 , A3 , A4 and A5 ) and T32 ( T1 , T2 , T3 , T4 and T5 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	0	1	i	1	D	0	0	0	imm3			Vd				0	x	x	0	0	Q	0	1	imm4
																				cmode						op

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VMOV{<c>}{<q>}.I32 <Dd>, #<imm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VMOV{<c>}{<q>}.I32 <Qd>, #<imm>

Decode for all variants of this encoding

if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)"; if op == '1' && cmode != '1110' then SEE "Related encodings"; if Q == '1' && Vd<0> == '1' then UNDEFINED; constant advsimd = TRUE; constant integer esize = 64; constant bits(esize) imm = AdvSIMDExpandImm(op, cmode, i:imm3:imm4); constant d = UInt(D:Vd); constant regs = if Q == '0' then 1 else 2;

A2

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				1	1	1	0	1	D	1	1	imm4H				Vd				1	0	size		(0)	0	(0)	0	imm4L
cond

Decode for all variants of this encoding

if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; if size == '01' && cond != '1110' then UNPREDICTABLE; constant integer esize = 8 << UInt(size); constant bits(esize) imm = VFPExpandImm(imm4H:imm4L, esize); constant advsimd = FALSE; constant integer d = if size == '11' then UInt(D:Vd) else UInt(Vd:D); constant integer regs = if size == '11' then 1 else 0;

CONSTRAINED UNPREDICTABLE behavior

If size == '01' && cond != '1110', then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.

A3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	0	1	i	1	D	0	0	0	imm3			Vd				1	0	x	0	0	Q	0	1	imm4
																				cmode						op

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VMOV{<c>}{<q>}.I16 <Dd>, #<imm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VMOV{<c>}{<q>}.I16 <Qd>, #<imm>

Decode for all variants of this encoding

A4

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	0	1	i	1	D	0	0	0	imm3			Vd				1	1	x	x	0	Q	0	1	imm4
																				cmode						op

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VMOV{<c>}{<q>}.<dt> <Dd>, #<imm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VMOV{<c>}{<q>}.<dt> <Qd>, #<imm>

Decode for all variants of this encoding

A5

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	0	1	i	1	D	0	0	0	imm3			Vd				1	1	1	0	0	Q	1	1	imm4
																				cmode						op

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VMOV{<c>}{<q>}.I64 <Dd>, #<imm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VMOV{<c>}{<q>}.I64 <Qd>, #<imm>

Decode for all variants of this encoding

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	i	1	1	1	1	1	D	0	0	0	imm3			Vd				0	x	x	0	0	Q	0	1	imm4
																				cmode						op

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VMOV{<c>}{<q>}.I32 <Dd>, #<imm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VMOV{<c>}{<q>}.I32 <Qd>, #<imm>

Decode for all variants of this encoding

T2

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	1	1	1	0	1	D	1	1	imm4H				Vd				1	0	size		(0)	0	(0)	0	imm4L

Encoding for the Half-precision scalar variant
(FEAT_FP16)

Applies when (size == 01)

VMOV{<c>}{<q>}.F16 <Sd>, #<imm>

Encoding for the Single-precision scalar variant

Applies when (size == 10)

VMOV{<c>}{<q>}.F32 <Sd>, #<imm>

Encoding for the Double-precision scalar variant

Applies when (size == 11)

VMOV{<c>}{<q>}.F64 <Dd>, #<imm>

Decode for all variants of this encoding

if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; if size == '01' && InITBlock() then UNPREDICTABLE; constant integer esize = 8 << UInt(size); constant bits(esize) imm = VFPExpandImm(imm4H:imm4L, esize); constant advsimd = FALSE; constant integer d = if size == '11' then UInt(D:Vd) else UInt(Vd:D); constant integer regs = if size == '11' then 1 else 0;

CONSTRAINED UNPREDICTABLE behavior

If size == '01' && InITBlock(), then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as if it passes the Condition code check.
The instruction executes as NOP. This means it behaves as if it fails the Condition code check.

T3

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	i	1	1	1	1	1	D	0	0	0	imm3			Vd				1	0	x	0	0	Q	0	1	imm4
																				cmode						op

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VMOV{<c>}{<q>}.I16 <Dd>, #<imm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VMOV{<c>}{<q>}.I16 <Qd>, #<imm>

Decode for all variants of this encoding

T4

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	i	1	1	1	1	1	D	0	0	0	imm3			Vd				1	1	x	x	0	Q	0	1	imm4
																				cmode						op

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VMOV{<c>}{<q>}.<dt> <Dd>, #<imm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VMOV{<c>}{<q>}.<dt> <Qd>, #<imm>

Decode for all variants of this encoding

T5

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	i	1	1	1	1	1	D	0	0	0	imm3			Vd				1	1	1	0	0	Q	1	1	imm4
																				cmode						op

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VMOV{<c>}{<q>}.I64 <Dd>, #<imm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VMOV{<c>}{<q>}.I64 <Qd>, #<imm>

Decode for all variants of this encoding

Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.

Assembler Symbols

<c>	For encoding A1, A3, A4 and A5: see Standard assembler syntax fields. This encoding must be unconditional.
	For encoding A2, T1, T2, T3, T4 and T5: see Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<dt>

The data type, encoded in cmode:

cmode	<dt>
110x	I32
1110	I8
1111	F32

<Qd>	Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Dd>	Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Sd>	Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<imm>	For encoding A1, A3, A4, A5, T1, T3, T4 and T5: is a constant of the specified type that is replicated to fill the destination register. For details of the range of constants available and the encoding of <imm>, see Modified immediate constants in T32 and A32 Advanced SIMD instructions.
	For encoding A2 and T2: is a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision, encoded in "imm4H:imm4L". For details of the range of constants available and the encoding of <imm>, see Modified immediate constants in T32 and A32 floating-point instructions.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDOrVFPEnabled(TRUE, advsimd); if esize <= 32 then S[d] = ZeroExtend(imm, 32); else for r = 0 to regs-1 D[d+r] = ZeroExtend(imm, 64);

Operational information

If CPSR.DIT is 1 and this instruction passes its condition execution check:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54