Vector Pairwise Add (floating-point) adds adjacent pairs of elements of two vectors, and places the results in the destination vector.
The operands and result are doubleword vectors.
The operand and result elements are floating-point numbers.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | D | 0 | sz | Vn | Vd | 1 | 1 | 0 | 1 | N | Q | M | 0 | Vm | |||||||||
if Q == '1' then UNDEFINED; if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; constant integer esize = 32 >> UInt(sz); constant integer elements = 64 DIV esize; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | D | 0 | sz | Vn | Vd | 1 | 1 | 0 | 1 | N | Q | M | 0 | Vm | |||||||||
if Q == '1' then UNDEFINED; if sz == '1' && !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; if sz == '1' && InITBlock() then UNPREDICTABLE; constant integer esize = 32 >> UInt(sz); constant integer elements = 64 DIV esize; constant d = UInt(D:Vd); constant n = UInt(N:Vn); constant m = UInt(M:Vm);
If sz == '1' && InITBlock(), then one of the following behaviors must occur:
| <c> |
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. |
|
For encoding T1: see Standard assembler syntax fields. |
| <q> |
| <dt> |
Is the data type for the elements of the vectors,
encoded in
|
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
| <Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
| <Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); constant FPCR_Type fpcr = StandardFPCR(); bits(64) dest; constant h = elements DIV 2; for e = 0 to h-1 Elem[dest,e,esize] = FPAdd(Elem[D[n],2*e,esize], Elem[D[n],2*e+1,esize], fpcr); Elem[dest,e+h,esize] = FPAdd(Elem[D[m],2*e,esize], Elem[D[m],2*e+1,esize], fpcr); D[d] = dest;
Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54
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