Vector Shift Left Long takes each element in a doubleword vector, left shifts them by an immediate value, and places the results in a quadword vector.
The operand elements can be:
The result elements are twice the length of the operand elements.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .
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| 1 | 1 | 1 | 1 | 0 | 0 | 1 | U | 1 | D | imm6 | Vd | 1 | 0 | 1 | 0 | 0 | 0 | M | 1 | Vm | |||||||||||
if imm6 == '000xxx' then SEE "Related encodings"; if imm6 IN {'001000', '010000', '100000'} then SEE "VMOVL"; if Vd<0> == '1' then UNDEFINED; constant integer esize = 8 << HighestSetBit(imm6<5:3>); constant integer elements = 64 DIV esize; constant integer shift_amount = UInt(imm6) - esize; constant unsigned = (U == '1'); constant d = UInt(D:Vd); constant m = UInt(M:Vm);
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| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | D | 1 | 1 | size | 1 | 0 | Vd | 0 | 0 | 1 | 1 | 0 | 0 | M | 0 | Vm | |||||||
if size == '11' || Vd<0> == '1' then UNDEFINED; constant integer esize = 8 << UInt(size); constant elements = 64 DIV esize; constant shift_amount = esize; constant unsigned = FALSE; // Or TRUE without change of functionality constant d = UInt(D:Vd); constant m = UInt(M:Vm);
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| 1 | 1 | 1 | U | 1 | 1 | 1 | 1 | 1 | D | imm6 | Vd | 1 | 0 | 1 | 0 | 0 | 0 | M | 1 | Vm | |||||||||||
if imm6 == '000xxx' then SEE "Related encodings"; if imm6 IN {'001000', '010000', '100000'} then SEE "VMOVL"; if Vd<0> == '1' then UNDEFINED; constant integer esize = 8 << HighestSetBit(imm6<5:3>); constant integer elements = 64 DIV esize; constant integer shift_amount = UInt(imm6) - esize; constant unsigned = (U == '1'); constant d = UInt(D:Vd); constant m = UInt(M:Vm);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | D | 1 | 1 | size | 1 | 0 | Vd | 0 | 0 | 1 | 1 | 0 | 0 | M | 0 | Vm | |||||||
if size == '11' || Vd<0> == '1' then UNDEFINED; constant integer esize = 8 << UInt(size); constant elements = 64 DIV esize; constant shift_amount = esize; constant unsigned = FALSE; // Or TRUE without change of functionality constant d = UInt(D:Vd); constant m = UInt(M:Vm);
Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.
| <c> |
For encoding A1 and A2: see Standard assembler syntax fields. This encoding must be unconditional. |
|
For encoding T1 and T2: see Standard assembler syntax fields. |
| <q> |
| <Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
| <Dm> |
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field. |
| <imm> |
The immediate value. <imm> must lie in the range 1 to <size>, and:
|
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); for e = 0 to elements-1 constant result = Int(Elem[Din[m],e,esize], unsigned) << shift_amount; Elem[Q[d>>1],e,2*esize] = result<2*esize-1:0>;
If CPSR.DIT is 1 and this instruction passes its condition execution check:
Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54
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