Vector Shift Right copies the contents of one SIMD register to another.
This is a pseudo-instruction of VORR (register). This means:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | D | 1 | 0 | Vn | Vd | 0 | 0 | 0 | 1 | N | Q | M | 1 | Vm | |||||||||
VSHR{<c>}{<q>}.<dt> <Dd>, <Dm>, #0
is equivalent to
VSHR{<c>}{<q>}.<dt> <Qd>, <Qm>, #0
is equivalent to
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | D | 1 | 0 | Vn | Vd | 0 | 0 | 0 | 1 | N | Q | M | 1 | Vm | |||||||||
VSHR{<c>}{<q>}.<dt> <Dd>, <Dm>, #0
is equivalent to
VSHR{<c>}{<q>}.<dt> <Qd>, <Qm>, #0
is equivalent to
| <c> |
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. |
|
For encoding T1: see Standard assembler syntax fields. |
| <q> |
| <dt> |
Is the data type for the elements of the vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64. |
| <Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
| <Qm> |
Is the 128-bit name of the SIMD&FP source register, encoded in the "N:Vn" and "M:Vm" field as <Qm>*2. |
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
| <Dm> |
Is the 64-bit name of the SIMD&FP source register, encoded in the "N:Vn" and "M:Vm" field. |
The description of VORR (register) gives the operational pseudocode for this instruction.
Internal version only: isa v01_32, pseudocode v2024-12_rel ; Build timestamp: 2024-12-16T10:54
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