The DC CIPAPA characteristics are:
Clean and Invalidate data cache by physical address to the Point of Physical Aliasing.
This instruction cleans and invalidates all copies of the Location specified in the Xt argument, irrespective of any MECID associated with the Location. Memory accesses resulting from the Clean operation use the MECID associated with the cache entry.
This instruction is present only when FEAT_RME is implemented. Otherwise, direct accesses to DC CIPAPA are UNDEFINED.
DC CIPAPA is a 64-bit System instruction.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NS | NSE | RES0 | PA[55:52] | PA | |||||||||||||||||||||||||||
| PA | |||||||||||||||||||||||||||||||
Together with the NSE field, this field specifies the target physical address space.
| NSE | NS | Meaning |
|---|---|---|
| 0b0 | 0b0 | When Secure state is implemented, Secure. Otherwise reserved. |
| 0b0 | 0b1 | Non-secure. |
| 0b1 | 0b0 | Root. |
| 0b1 | 0b1 | Realm. |
If FEAT_SEL2 is not implemented, and {NSE, NS} == {0b0, 0b0}, then no cache entries are required to be cleaned or invalidated
Together with the NS field, this field specifies the target physical address space.
For a description of the values derived by evaluating NS and NSE together, see DC CIPAPA.NS.
Reserved, RES0.
Extension to PA[51:0] if ID_AA64MMFR0_EL1.PARange = 0111. For more information see PA[51:0].
Reserved, RES0.
Physical address to use. No alignment restrictions apply to this PA.
This instruction is not subject to any translation, permission checks, or granule protection checks.
This instruction affects all caches in the Outer Shareable shareability domain.
This instruction has the same ordering, observability, and completion behavior as VA-based cache maintenance instructions issued to the Outer Shareable shareability domain.
Accesses to this instruction use the following encodings in the System instruction encoding space:
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b01 | 0b110 | 0b0111 | 0b1110 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then AArch64.DC(X[t, 64], CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoPA);
04/07/2023 11:22; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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