The ICV_CTLR_EL1 characteristics are:
Controls aspects of the behavior of the GIC virtual CPU interface and provides information about the features implemented.
AArch64 System register ICV_CTLR_EL1 bits [31:0] are architecturally mapped to AArch32 System register ICV_CTLR[31:0].
This register is present only when FEAT_GICv3 is implemented and EL2 is implemented. Otherwise, direct accesses to ICV_CTLR_EL1 are UNDEFINED.
ICV_CTLR_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | ExtRange | RSS | RES0 | A3V | SEIS | IDbits | PRIbits | RES0 | EOImode | CBPR |
Reserved, RES0.
Extended INTID range (read-only).
ExtRange | Meaning |
---|---|
0b0 | CPU interface does not support INTIDs in the range 1024..8191.
Note Arm strongly recommends that the IRI is not configured to deliver interrupts in this range to a PE that does not support them. |
0b1 | CPU interface supports INTIDs in the range 1024..8191
|
ICV_CTLR_EL1.ExtRange is an alias of ICC_CTLR_EL1.ExtRange.
Range Selector Support. Possible values are:
RSS | Meaning |
---|---|
0b0 |
Targeted SGIs with affinity level 0 values of 0 - 15 are supported. |
0b1 |
Targeted SGIs with affinity level 0 values of 0 - 255 are supported. |
This bit is read-only.
Reserved, RES0.
Affinity 3 Valid. Read-only and writes are ignored. Possible values are:
A3V | Meaning |
---|---|
0b0 |
The virtual CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers. |
0b1 |
The virtual CPU interface logic supports nonzero values of Affinity 3 in SGI generation System registers. |
SEI Support. Read-only and writes are ignored. Indicates whether the virtual CPU interface supports local generation of SEIs:
SEIS | Meaning |
---|---|
0b0 |
The virtual CPU interface logic does not support local generation of SEIs. |
0b1 |
The virtual CPU interface logic supports local generation of SEIs. |
Identifier bits. Read-only and writes are ignored. The number of virtual interrupt identifier bits supported:
IDbits | Meaning |
---|---|
0b000 |
16 bits. |
0b001 |
24 bits. |
All other values are reserved.
Indicates the number of virtual priority bits implemented.
An implementation must implement at least 32 levels of virtual priority (5 priority bits).
The division between group priority and subpriority is defined in the binary point registers ICV_BPR0_EL1 and ICV_BPR1_EL1.
The value of this field is an IMPLEMENTATION DEFINED choice of:
PRIbits | Meaning |
---|---|
0b100..0b110 |
The number of virtual priority bits implemented, minus one. |
Access to this field is RO.
Reserved, RES0.
Virtual EOI mode. Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt:
EOImode | Meaning |
---|---|
0b0 |
ICV_EOIR0_EL1 and ICV_EOIR1_EL1 provide both priority drop and interrupt deactivation functionality. Accesses to ICV_DIR_EL1 are UNPREDICTABLE. |
0b1 |
ICV_EOIR0_EL1 and ICV_EOIR1_EL1 provide priority drop functionality only. ICV_DIR_EL1 provides interrupt deactivation functionality. |
The reset behavior of this field is:
Common Binary Point Register. Controls whether the same register is used for interrupt preemption of both virtual Group 0 and virtual Group 1 interrupts:
CBPR | Meaning |
---|---|
0b0 |
ICV_BPR1_EL1 determines the preemption group for virtual Group 1 interrupts. |
0b1 | Non-secure reads of ICV_BPR1_EL1 return ICV_BPR0_EL1 plus one, saturated to 0b111. Non-secure writes to ICV_BPR1_EL1 are ignored. Secure reads of ICV_BPR1_EL1 return ICV_BPR0_EL1. Secure writes of ICV_BPR1_EL1 modify ICV_BPR0_EL1. |
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1100 | 0b1100 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.<IRQ,FIQ> == '11' then UNDEFINED; elsif ICC_SRE_EL1.SRE == '0' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.FMO == '1' then X[t, 64] = ICV_CTLR_EL1; elsif EL2Enabled() && HCR_EL2.IMO == '1' then X[t, 64] = ICV_CTLR_EL1; elsif HaveEL(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then X[t, 64] = ICC_CTLR_EL1_S; else X[t, 64] = ICC_CTLR_EL1_NS; else X[t, 64] = ICC_CTLR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.<IRQ,FIQ> == '11' then UNDEFINED; elsif ICC_SRE_EL2.SRE == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then X[t, 64] = ICC_CTLR_EL1_S; else X[t, 64] = ICC_CTLR_EL1_NS; else X[t, 64] = ICC_CTLR_EL1; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3.SRE == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else if SCR_EL3.NS == '0' then X[t, 64] = ICC_CTLR_EL1_S; else X[t, 64] = ICC_CTLR_EL1_NS;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1100 | 0b1100 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.<IRQ,FIQ> == '11' then UNDEFINED; elsif ICC_SRE_EL1.SRE == '0' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2.TC == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.FMO == '1' then ICV_CTLR_EL1 = X[t, 64]; elsif EL2Enabled() && HCR_EL2.IMO == '1' then ICV_CTLR_EL1 = X[t, 64]; elsif HaveEL(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then ICC_CTLR_EL1_S = X[t, 64]; else ICC_CTLR_EL1_NS = X[t, 64]; else ICC_CTLR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.<IRQ,FIQ> == '11' then UNDEFINED; elsif ICC_SRE_EL2.SRE == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then ICC_CTLR_EL1_S = X[t, 64]; else ICC_CTLR_EL1_NS = X[t, 64]; else ICC_CTLR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3.SRE == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else if SCR_EL3.NS == '0' then ICC_CTLR_EL1_S = X[t, 64]; else ICC_CTLR_EL1_NS = X[t, 64];
04/07/2023 11:26; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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