The ISR_EL1 characteristics are:
Shows the pending status of IRQ and FIQ interrupts and SError exceptions.
When FEAT_NMI is implemented, also shows whether a pending IRQ or FIQ interrupt has Superpriority.
AArch64 System register ISR_EL1 bits [31:0] are architecturally mapped to AArch32 System register ISR[31:0].
ISR_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | IS | FS | A | I | F | RES0 |
Reserved, RES0.
IRQ with Superpriority pending bit. Indicates whether an IRQ interrupt with Superpriority is pending.
IS | Meaning |
---|---|
0b0 |
No pending IRQ with Superpriority. |
0b1 |
An IRQ interrupt with Superpriority is pending. |
If all of the following apply then this field shows the pending status of virtual IRQ interrupts with Superpriority:
Otherwise, this field shows the pending status of physical IRQ interrupts with Superpriority.
Reserved, RES0.
FIQ with Superpriority pending bit. Indicates whether an FIQ interrupt with Superpriority is pending.
FS | Meaning |
---|---|
0b0 |
No pending FIQ with Superpriority. |
0b1 |
An FIQ interrupt with Superpriority is pending. |
If all of the following apply then this field shows the pending status of virtual FIQ interrupts with Superpriority:
Otherwise, this field shows the pending status of physical FIQ interrupts with Superpriority.
Reserved, RES0.
SError exception pending bit. Indicates whether an SError exception is pending.
A | Meaning |
---|---|
0b0 |
No pending SError. |
0b1 |
An SError exception is pending. |
If all of the following apply then this field shows the pending status of virtual SError exceptions:
Otherwise, this field shows the pending status of physical SError exceptions.
If the physical SError exception is edge-triggered, this field is cleared to zero when the physical SError exception is taken.
IRQ pending bit. Indicates whether an IRQ interrupt is pending.
I | Meaning |
---|---|
0b0 |
No pending IRQ. |
0b1 |
An IRQ interrupt is pending. |
If all of the following apply then this field shows the pending status of virtual IRQ interrupts:
Otherwise, this field shows the pending status of physical IRQ interrupts.
This bit indicates the presence of a pending IRQ interrupt regardless of whether the interrupt has Superpriority.
FIQ pending bit. Indicates whether an FIQ interrupt is pending.
F | Meaning |
---|---|
0b0 |
No pending FIQ. |
0b1 |
An FIQ interrupt is pending. |
If all of the following apply then this field shows the pending status of virtual FIQ interrupts:
Otherwise, this field shows the pending status of physical FIQ interrupts.
This bit indicates the presence of a pending FIQ interrupt regardless of whether the interrupt has Superpriority.
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1100 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.ISR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ISR_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ISR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ISR_EL1;
04/07/2023 11:25; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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