The AMDEVAFF0 characteristics are:
Copy of the low half of the PE MPIDR_EL1 register that allows a debugger to determine which PE in a multiprocessor system the AMU component relates to.
It is IMPLEMENTATION DEFINED whether AMDEVAFF0 is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMUv1 is implemented, FEAT_AMU_EXT32 is implemented and an implementation implements AMDEVAFF0. Otherwise, direct accesses to AMDEVAFF0 are RES0.
AMDEVAFF0 is a 32-bit register.
This register is part of the AMU block.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPIDR_EL1lo | |||||||||||||||||||||||||||||||
MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1, as seen from the highest implemented Exception level.
Accesses to this register use the following encodings:
Accesses on this interface are RO.
04/07/2023 11:27; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.