The AMEVCNTR1<n> characteristics are:
Provides access to the auxiliary activity monitor event counters.
External register AMEVCNTR1<n> bits [63:0] are architecturally mapped to AArch64 System register AMEVCNTR1<n>_EL0[63:0].
External register AMEVCNTR1<n> bits [31:0] are architecturally mapped to AArch32 System register AMEVCNTR1<n>[31:0].
It is IMPLEMENTATION DEFINED whether AMEVCNTR1<n> is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMEVCNTR1<n> are RES0.
AMEVCNTR1<n> is a 64-bit register.
This register is part of the AMU block.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACNT | |||||||||||||||||||||||||||||||
| ACNT | |||||||||||||||||||||||||||||||
Auxiliary activity monitor event counter n.
Value of auxiliary activity monitor event counter n, where n is the number of this register and is a number from 0 to 15.
The reset behavior of this field is:
If <n> is greater than or equal to the number of auxiliary activity monitor event counters, reads of AMEVCNTR1<n> are RAZ. Software must treat reserved accesses as RES0. See 'Access requirements for reserved and unallocated registers'.
AMCGCR.CG1NC identifies the number of auxiliary activity monitor event counters.
Accesses to this register use the following encodings:
Accesses on this interface are RO.
Accesses on this interface are RO.
04/07/2023 11:27; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.