The GICD_CLRSPI_NSR characteristics are:
Removes the pending state from a valid SPI if permitted by the Security state of the access and the GICD_NSACR<n> value for that SPI.
A write to this register changes the state of a pending SPI to inactive, and the state of an active and pending SPI to active.
If GICD_TYPER.MBIS == 0, this register is reserved.
When GICD_CTLR.DS == 1, this register provides functionality for all SPIs.
GICD_CLRSPI_NSR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | INTID |
Reserved, RES0.
The INTID of the SPI.
The function of this register depends on whether the targeted SPI is configured to be an edge-triggered or level-sensitive interrupt:
Writes to this register have no effect if:
16-bit accesses to bits [15:0] of this register must be supported.
A Secure access to this register can clear the pending state of any valid SPI.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Distributor | Dist_base | 0x0048 | GICD_CLRSPI_NSR |
Accesses on this interface are WO.
04/07/2023 11:25; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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