GICD_ISPENDR<n>E, Interrupt Set-Pending Registers (extended SPI range), n = 0 - 31

The GICD_ISPENDR<n>E characteristics are:

Purpose

Adds the pending state to the corresponding SPI in the extended SPI range.

This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICD_ISPENDR<n>E are RES0.

When GICD_TYPER.ESPI==0, these registers are RES0.

When GICD_TYPER.ESPI==1, the number of implemented GICD_ISPENDR<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0.

GICD_ISPENDR<n>E is a 32-bit register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Set_pending_bit31	Set_pending_bit30	Set_pending_bit29	Set_pending_bit28	Set_pending_bit27	Set_pending_bit26	Set_pending_bit25	Set_pending_bit24	Set_pending_bit23	Set_pending_bit22	Set_pending_bit21	Set_pending_bit20	Set_pending_bit19	Set_pending_bit18	Set_pending_bit17	Set_pending_bit16	Set_pending_bit15	Set_pending_bit14	Set_pending_bit13	Set_pending_bit12	Set_pending_bit11	Set_pending_bit10	Set_pending_bit9	Set_pending_bit8	Set_pending_bit7	Set_pending_bit6	Set_pending_bit5	Set_pending_bit4	Set_pending_bit3	Set_pending_bit2	Set_pending_bit1	Set_pending_bit0

For the extended SPIs, adds the pending state to interrupt number x. Reads and writes have the following behavior:

Set_pending_bit<x>	Meaning
0b0	If read, indicates that the corresponding interrupt is not pending. If written, has no effect.
0b1	If read, indicates that the corresponding interrupt is pending, or active and pending. If written, changes the state of the corresponding interrupt from inactive to pending, or from active to active and pending. This has no effect in the following cases: If the interrupt is already pending because of a write to GICD_ISPENDR<n>E. If the interrupt is already pending because the corresponding interrupt signal is asserted. In this case, the interrupt remains pending if the interrupt signal is deasserted.

Set_pending_bit<x>

Meaning

0b0

If read, indicates that the corresponding interrupt is not pending.

If written, has no effect.

0b1

If read, indicates that the corresponding interrupt is pending, or active and pending.

If written, changes the state of the corresponding interrupt from inactive to pending, or from active to active and pending.

This has no effect in the following cases:

If the interrupt is already pending because of a write to GICD_ISPENDR<n>E.
If the interrupt is already pending because the corresponding interrupt signal is asserted. In this case, the interrupt remains pending if the interrupt signal is deasserted.

The reset behavior of this field is:

For INTID m, when DIV and MOD are the integer division and modulo operations:

The corresponding GICD_ISPENDR<n>E number, n, is given by n = (m-4096) DIV 32.
The offset of the required GICD_ISPENDR<n>E is (0x1600 + (4*n)).
The bit number of the required group modifier bit in this register is (m-4096) MOD 32.

When affinity routing is not enabled for the Security state of an interrupt in GICD_ISPENDR<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

Component	Frame	Offset	Instance
GIC Distributor	Dist_base	0x1600 + (4 * n)	GICD_ISPENDR<n>E

Accesses on this interface are RW.

04/07/2023 11:25; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68