DSPSR2, Debug Saved Process State Register 2

The DSPSR2 characteristics are:

Purpose

Holds the saved process state for Debug state. On entering Debug state, PSTATE information is written to this register. On exiting Debug state, values are copied from this register to PSTATE.

Configuration

AArch32 System register DSPSR2 bits [31:0] are architecturally mapped to AArch64 System register DSPSR_EL0[63:32].

This register is present only when FEAT_Debugv8p9 is implemented and AArch32 is supported. Otherwise, direct accesses to DSPSR2 are UNDEFINED.

Attributes

DSPSR2 is a 32-bit register.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																														PPEND	RES0

Bits [31:2]

Reserved, RES0.

PPEND, bit [1]
When FEAT_SEBEP is implemented:

PMU exception pending. Set to the value of PSTATE.PPEND on entering Debug state, and copied to PSTATE.PPEND on exiting Debug state.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Reserved, RES0.

Bit [0]

Reserved, RES0.

Accessing DSPSR2

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b011	0b0100	0b0101	0b010

if !Halted() then UNDEFINED; else R[t] = DSPSR2;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b011	0b0100	0b0101	0b010

if !Halted() then UNDEFINED; else DSPSR2 = R[t];

15/03/2024 21:49; 3156453dc257d36c4630671c3d896bfc69048210

DSPSR2, Debug Saved Process State Register 2

Purpose

Configuration

Attributes

Field descriptions

Bits [31:2]

PPEND, bit [1]When FEAT_SEBEP is implemented:

Otherwise:

Bit [0]

Accessing DSPSR2

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

PPEND, bit [1]
When FEAT_SEBEP is implemented: