The AMCIDR0 characteristics are:
Provides information to identify an activity monitors component.
For more information, see 'About the Component identification scheme'.
It is IMPLEMENTATION DEFINED whether AMCIDR0 is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMUv1 is implemented and an implementation implements AMCIDR0. Otherwise, direct accesses to AMCIDR0 are RES0.
AMCIDR0 is a 32-bit register.
This register is part of the AMU block.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PRMBL_0 |
Reserved, RES0.
Preamble.
Reads as 0x0D.
Access to this field is RO.
Accesses to this register use the following encodings:
Accessible at offset 0xFF0 from AMU
Accesses on this interface are RO.
15/03/2024 21:50; 3156453dc257d36c4630671c3d896bfc69048210
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