The CTIPIDR1 characteristics are:
Provides information to identify a CTI component.
For more information, see 'About the Peripheral identification scheme'.
CTIPIDR1 is in the Debug power domain.
Implementation of this register is OPTIONAL.
This register is required for CoreSight compliance.
CTIPIDR1 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | DES_0 | PART_1 | |||||||||||||||||||||||||||||
Reserved, RES0.
Designer, least significant nibble of JEP106 ID code. For Arm Limited, this field is 0b1011.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Part number, most significant nibble.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
| Component | Offset | Instance |
|---|---|---|
| CTI | 0xFE4 | CTIPIDR1 |
Accesses on this interface are RO.
15/03/2024 21:50; 3156453dc257d36c4630671c3d896bfc69048210
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