EDCIDR1, External Debug Component Identification Register 1

The EDCIDR1 characteristics are:

Purpose

Provides information to identify an external debug component.

For more information, see 'About the Component Identification scheme'.

When FEAT_DoPD is implemented, EDCIDR1 is in the Core power domain. Otherwise, EDCIDR1 is in the Debug power domain.

Implementation of this register is OPTIONAL.

This register is required for CoreSight compliance.

EDCIDR1 is a 32-bit register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																								CLASS				PRMBL_1

Reserved, RES0.

Component class.

CLASS	Meaning
0b1001	CoreSight component.

Other values are defined by the CoreSight Architecture.

This field reads as 0x9.

Access to this field is RO.

Preamble.

Reads as 0b0000.

Access to this field is RO.

Component	Offset	Instance
Debug	0xFF4	EDCIDR1

This interface is accessible as follows:

When FEAT_DoPD is implemented and !IsCorePowered(), accesses to this register generate an error response.
Otherwise, accesses to this register are RO.

15/03/2024 21:50; 3156453dc257d36c4630671c3d896bfc69048210